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Showing results 1 to 20 of 35

Issue DateTitleAuthor(s)TypeView
2017-05-22A Novel Ternary Multiplier based on Ternary CMOS Compact ModelKang, Yesung; Kim, Jaewoo; Kim, Sunmin; Shin, Sunhae; Jang, E-San; Jeong, Jae Won; Kim, Kyung Rok; Kang, SeokhyeongCONFERENCE77
2016-02-23Advanced bulk CMOS technology-based standard ternary inverter for compact multi-valued analog-to-digital converterShin, Sunhae; Kyung Rok KimCONFERENCE30
2017-05-22CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic CircuitsShin, Sunhae; Jang, Esan; Jeong, Jae Won; Kim, Kyung RokCONFERENCE56
2018-02-05Common Body for Ternary CMOS Logic Gates for Endurance of the Input Pattern Effects on Intermediate State LevelJang, Esan; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung RokCONFERENCE46
2016-02-23Compact CMOS-based multi-valued literal gate as a building block for multi valued logic and memory applicationsJang, E-San; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung RokCONFERENCE45
2015-08Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS TechnologyShin, Sunhae; Jang, Esan; Jeong, Jae Won; Park, Byung-Gook; Kim, Kyung RokARTICLE882
2017-02-15Compact Model for Positive Gain-Embedded Voltage Transfer Curve of Inverter Based on Novel I-V Curves for Multi-Peak NDRJeong, Jaewon; Shin, Sunhae; Jang, Esan; Kim, Kyung RokCONFERENCE30
2016-06-12Demonstration of standrad ternary inverter based on CMOS technologyShin, Sunhae; Jang, Esan; Jeong, Jae Won; Kim, Kyung RokCONFERENCE60
2016-06-12Device optimization on gate oxide and spacer dielectric permittivity for 'well-tempered' nanoscale MOSFETJang, Esan; Shin, Sunhae; Jung, Jae Won; Jung, Yu Jung; Kim, Kyung RokCONFERENCE38
2012-06Extraction Method for Substrate-Related Components of Vertical Junctionless Silicon Nanowire Field-Effect Transistors and Its Verification on Radio Frequency CharacteristicsShin, Sunhae; Kang, In Man; Kim, Kyung RokARTICLE682
2015-06Gate induced drain leakage reduction with analysis of gate fringing field effect on high-kappa/metal gate CMOS technologyJang, Esan; Shin, Sunhae; Jung, Jae Won; Kim, Kyung RokARTICLE741
2017-07-03Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-k Spacer TechnologyJang, E-San; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung RokCONFERENCE120
2018-06Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-kappa Spacer TechnologyJang, Esan; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung RokARTICLE346
2017-02-14Low leakage III-V/Ge CMOS FinFET design with high-k spacer technologyJang, E-San; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung RokCONFERENCE44
2015-07-02Multi-Valued Logic Based on CMOS technologyKim, Kyung Rok; Shin, Sunhae; Jang, Esan; Jung, Jae WonCONFERENCE40
2015-02-11Multiple Negative Differential Resistance Device by Using the Ambipolar Behavior of TFET with Fast Switching CharacteristicsJeong, Jae Won; Shin, Sunhae; Jang, E-san; Kim, Kyung RokCONFERENCE53
2016-05Multiple Negative Differential Resistance Device by Using the Ambipolar Behavior of Tunneling Field Effect Transistor with Fast Switching CharacteristicsJeong, Jae Won; Jang, E-San; Shin, Sunhae; Kim, Kyung RokARTICLE1843
2015-06Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applicationsShin, Sunhae; Kim, Kyung RokARTICLE852
2013-02-04Negative Differential Resistance Devices with Ultra-High Peak-to-Valley Current Ratio and Its Multiple Switching CharacteristicsShin, Sunhae; Kim, Kyung RokCONFERENCE32
2013-12Negative differential resistance devices with ultra-high peak-to-valley current ratio and its multiple switching characteristicsShin, Sunhae; Kang, In Man; Kim, Kyung RokARTICLE835
Showing results 1 to 20 of 35

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