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- Kim, Kyung Rok
- Nano-Electronic Emerging Devices Lab.
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Standard Ternary Inverter Based on Junction Leakage-Enhanced Nanoscale Planar CMOS and Its Variation Immunity
- Author(s)
- Kim, Kyung Rok, Shin, Sunhae, Jang, Esan
- Issued Date
- 2014-06-08
- Citation
- Silicon Nanoelectronics Workshop, SNW 2014
- Abstract
- We propose a novel standard ternary inverter (STI) based on nanoscale planar CMOS technology for a compact design of multi-valued logic (MVL). By enhancing junction band-to-band tunneling (BTBT) leakage with high channel doping for STI operation, the 'third' intermediate state (VINT) can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. It is demonstrated that the variability of the intermediate level (ΔVINT<80mV) can be allowable into the worst noise margin (>0.1V).
- Publisher
- Silicon Nanoelectronics Workshop, SNW 2014
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