Ultra-Low Power Ternary CMOS Platform for Physical Synthesis of Multi-Valued Logic and Memory Applications

Abstract

Motivation of this work is to provide feasible, scalable, and designable multi-valued logic (MVL) device platform for physical synthesis of MVL circuits. Especially, ternary device and its general logic functions are focused, owing to most efficiently reduced circuit complexity per radix (R) increase. By designing the OFF-state constant current, not only the standby power (PS) issue of additional intermediate state is overcome, but also continuous supply voltage (VDD) scaling and dynamic power (PD) scaling are possible owing to single-step I-V characteristics. By applying a novel ternary device concept to CMOS technology with OFF-state current mechanism of band-to-band tunneling (BTBT) currents (IBTBT) and subthreshold diffusion current (Isub), the logic changes from binary to ternary are confirmed using mixed-mode device simulation. I experimentally demonstrate ternary CMOS (T-CMOS) and verified its low-power standard ternary inverter (STI) operation by designing channel profiles in conventional binary CMOS. The realized complementary ternary n/pMOS (T-n/pMOS) have fully gate bias (VG)-independent and symmetrical IBTBT of ~10 pA/m based on proven ion-implantation process, which produces stable and designable intermediate state (VOM) at exactly VDD/2. To present T-CMOS design frameworks in terms of static noise margin (SNM) enhancement and ultra-low power operation, I develop the compact model of T-CMOS and verify the physical model parameters with experimental data. Through the feasible design of Isub with abrupt channel profile based on low thermal budget process, STI has a SNM of 283 mV (80 % of ideal SNM) at VDD= 1V operation and intermediate state stability of ΔVOM < ± 0.1V, even considering the random-dopant fluctuation (RDF) of 32 nm and 22 nm technology. Continuous VDD scaling below 0.5V (SNM= 40% at VDD = 0.3V) enables STI operation with ultra-low PD and PS based on exponentially reduced IBTBT currents. As MVL and memory (MVM) applications, minimum(MIN)/maximum(MAX) gates, analog-to-digital converter (ADC) circuit, and 5-state latch are studied with T-CMOS compact model. Especially ADC circuits revolutionary decreases number of device and circuit interconnection with 9.6% area of binary system.