Multi-Valued Logic Based on CMOS technology

Abstract

We propose a novel standard ternary inverter (STI) based on nanoscale planar CMOS technology for a compact design of multi-valued logic (MVL). By enhancing junction band-to-band tunneling (BTBT) leakage with high channel doping for STI operation, the “third” intermediate state (VINT) can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. The junction BTBT off-leakage variation effects are investigated by considering doping fluctuation in the mixed-mode device simulation. It is demonstrated that the variability of the intermediate level (DVINT< 80 mV) can be allowable into the worst noise margin (> 0.1 V) of STI operation.