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Kim, Seong-Jin
Bio-inspired Microsystems Lab (BiML)
Research Interests
  • Integrated analog-mixed signal circuit design, semiconductor sensor interface circuits

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Tunnelling-based ternary metal–oxide–semiconductor technology

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Title
Tunnelling-based ternary metal–oxide–semiconductor technology
Author
Jeong, Jae WonChoi, Young EunKim, Woo SeokPark, Jee-HoKim, SunmeanShin, SunhaeLee, KyuhoChang, JiwonKim, Seong-JinKim, Kyung Rok
Issue Date
2019-07
Publisher
NATURE PUBLISHING GROUP
Citation
NATURE ELECTRONICS, v.2, no.7, pp.307 - 3112
Abstract
The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.
URI
https://scholarworks.unist.ac.kr/handle/201301/26858
URL
https://www.nature.com/articles/s41928-019-0272-8
DOI
10.1038/s41928-019-0272-8
ISSN
2520-1131
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ECE_Journal Papers
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