Tunnelling-based ternary metal–oxide–semiconductor technology
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- Tunnelling-based ternary metal–oxide–semiconductor technology
- Jeong, Jae Won; Choi, Young Eun; Kim, Woo Seok; Park, Jee-Ho; Kim, Sunmean; Shin, Sunhae; Lee, Kyuho; Chang, Jiwon; Kim, Seong-Jin; Kim, Kyung Rok
- Issue Date
- NATURE PUBLISHING GROUP
- NATURE ELECTRONICS, v.2, no.7, pp.307 - 3112
- The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.
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