IEEE International Symposium on Multiple-Valued Logic, pp.284 - 289
Abstract
We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits. By developing the compact model of T-CMOS and verifying the physical model parameters with experimental data, the T-CMOS design framework based on standard ternary inverter (STI) is presented for static noise margin (SNM) enhancement and performance analysis of ternary logic gates.