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Kim, Kyung Rok
Nano-Electronic Emerging Devices Lab.
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Novel Tri-State Latch using Single-Peak Negative Differential Resistance Devices

Author(s)
Kim, Kyung RokShin, Sunhae
Issued Date
2014-06-09
DOI
10.1109/SNW.2014.7348610
URI
https://scholarworks.unist.ac.kr/handle/201301/46734
Fulltext
https://ieeexplore.ieee.org/document/7348610
Citation
Silicon Nanoelectronics Workshop, SNW 2014
Abstract
We propose a novel tri-state latch based on single-peak MOS-NDR. By shifting peak voltage over half of the supply voltage, tri-state memory can be implemented. The fully suppressed valley current of MOS-NDR guarantees the supply voltage design margin in tri-state logic and memory.
Publisher
Silicon Nanoelectronics Workshop, SNW 2014

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