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Showing results 1 to 20 of 44

Issue DateTitleAuthor(s)TypeView
2020-09A Logic Synthesis Methodology for Low-Power Ternary Logic CircuitsKim, Sunmean; Lee, Sung-Yun; Park, Sunghye; Kim, Kyung Rok; Kang, SeokhyeongARTICLE229
2018-02A Metaheuristic Method for Fast Multi-Deck LegalizationKang, Seokhyeong; Do, SangGiMaster's thesis510
2014-05-22A New Methodology for Reduced Cost of ResilienceKang, Seokhyeong; Kahng, Andrew B.; Li, JiajiaCONFERENCE128
2016-10-26A novel design methodology for error-resilient circuits in near-Threshold computingLee, Jaemin; Kim, Sunmean; Kim, Youngmin; Kang, SeokhyeongCONFERENCE203
2017-08A Novel Methodology for Error-Resilient Circuits in Near-Threshold ComputingKang, Seokhyeong; Lee, JaeminMaster's thesis396
2017-05-22A Novel Ternary Multiplier based on Ternary CMOS Compact ModelKang, Yesung; Kim, Jaewoo; Kim, Sunmin; Shin, Sunhae; Jang, E-San; Jeong, Jae Won; Kim, Kyung Rok; Kang, SeokhyeongCONFERENCE189
2017-08-30A preliminary analysis of domain coupling in package power distribution networkBae, Byoungjin; Kim, Seungwon; Kim, Youngmin; Kang, Seokhyeong; Kim, Il Joon; Kim, Kwangseok; Kang, Sunwon; Han, Ki JinCONFERENCE147
2012-06-05Accuracy-Configurable Adder for Approximate Arithmetic DesignsKahng, Andrew B.; Kang, SeokhyeongCONFERENCE103
2013-03-18Active-Mode Leakage Reduction with Data-Retained Power GatingKahng, Andrew B.; Kang, Seokhyeong; Park, BongilCONFERENCE106
2015-09An Improved Methodology for Resilient Design ImplementationKahng, Andrew B.; Kang, Seokhyeong; Li, Jiajia; De Gyvez, Jose PinedaARTICLE744
2018-01-22An optimal gate design for the synthesis of ternary logic circuitsKim, Sunmean; Lim, Taeho; Kang, SeokhyeongCONFERENCE114
2018-02An Optimal Gate Design for the Synthesis of Ternary Logic CircuitsKang, Seokhyeong; Kim, SunmeanMaster's thesis501
2015-10-05An optimal operating point by using error monitoring circuits with an error-resilient techniqueLee, Jaemin; Kim, Seungwon; Kim, Youngmin; Kang, SeokhyeongCONFERENCE140
2014-11-05Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV modelsKim, Seungwon; Han, Ki Jin; Kang, Seokhyeong; Kim, YoungminCONFERENCE123
2012-03-25Construction of Realistic Gate Sizing Benchmarks With Known Optimal SolutionsKang, Seokhyeong; Kahng, Andrew B.CONFERENCE103
2019-05-21Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary LogicKim, Sunmean; Lee, Sung-Yun; Park, Sunghye; Kang, SeokhyeongCONFERENCE180
2010-01-10Designing a Processor From the Ground Up to Allow Voltage/Reliability TradeoffsKang, Seokhyeong; Kahng, AB; Kumar, R; Sartori, JCONFERENCE118
2013-10Enhancing the Efficiency of Energy-Constrained DVFS DesignsKahng, Andrew B.; Kang, Seokhyeong; Kumar, Rakesh; Sartori, JohnARTICLE793
2018-03-19Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case studyKim, Seungwon; Han, Ki Jin; Kim, Youngmin; Kang, SeokhyeongCONFERENCE129
2017-06-20Fast Predictive Useful Skew Methodology for Timing-Driven Placement OptimizationKim, Seungwon; Do, SangGi; Kang, SeokhyeongCONFERENCE170
Showing results 1 to 20 of 44