| 2020-09 | A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits | Kim, Sunmean; Lee, Sung-Yun; Park, Sunghye; Kim, Kyung Rok; Kang, Seokhyeong | ARTICLE | 229 |
| 2018-02 | A Metaheuristic Method for Fast Multi-Deck Legalization | Kang, Seokhyeong; Do, SangGi | Master's thesis | 510 |
| 2014-05-22 | A New Methodology for Reduced Cost of Resilience | Kang, Seokhyeong; Kahng, Andrew B.; Li, Jiajia | CONFERENCE | 128 |
| 2016-10-26 | A novel design methodology for error-resilient circuits in near-Threshold computing | Lee, Jaemin; Kim, Sunmean; Kim, Youngmin; Kang, Seokhyeong | CONFERENCE | 203 |
| 2017-08 | A Novel Methodology for Error-Resilient Circuits in Near-Threshold Computing | Kang, Seokhyeong; Lee, Jaemin | Master's thesis | 396 |
| 2017-05-22 | A Novel Ternary Multiplier based on Ternary CMOS Compact Model | Kang, Yesung; Kim, Jaewoo; Kim, Sunmin; Shin, Sunhae; Jang, E-San; Jeong, Jae Won; Kim, Kyung Rok; Kang, Seokhyeong | CONFERENCE | 189 |
| 2017-08-30 | A preliminary analysis of domain coupling in package power distribution network | Bae, Byoungjin; Kim, Seungwon; Kim, Youngmin; Kang, Seokhyeong; Kim, Il Joon; Kim, Kwangseok; Kang, Sunwon; Han, Ki Jin | CONFERENCE | 147 |
| 2012-06-05 | Accuracy-Configurable Adder for Approximate Arithmetic Designs | Kahng, Andrew B.; Kang, Seokhyeong | CONFERENCE | 103 |
| 2013-03-18 | Active-Mode Leakage Reduction with Data-Retained Power Gating | Kahng, Andrew B.; Kang, Seokhyeong; Park, Bongil | CONFERENCE | 106 |
| 2015-09 | An Improved Methodology for Resilient Design Implementation | Kahng, Andrew B.; Kang, Seokhyeong; Li, Jiajia; De Gyvez, Jose Pineda | ARTICLE | 744 |
| 2018-01-22 | An optimal gate design for the synthesis of ternary logic circuits | Kim, Sunmean; Lim, Taeho; Kang, Seokhyeong | CONFERENCE | 114 |
| 2018-02 | An Optimal Gate Design for the Synthesis of Ternary Logic Circuits | Kang, Seokhyeong; Kim, Sunmean | Master's thesis | 501 |
| 2015-10-05 | An optimal operating point by using error monitoring circuits with an error-resilient technique | Lee, Jaemin; Kim, Seungwon; Kim, Youngmin; Kang, Seokhyeong | CONFERENCE | 140 |
| 2014-11-05 | Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV models | Kim, Seungwon; Han, Ki Jin; Kang, Seokhyeong; Kim, Youngmin | CONFERENCE | 123 |
| 2012-03-25 | Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions | Kang, Seokhyeong; Kahng, Andrew B. | CONFERENCE | 103 |
| 2019-05-21 | Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic | Kim, Sunmean; Lee, Sung-Yun; Park, Sunghye; Kang, Seokhyeong | CONFERENCE | 180 |
| 2010-01-10 | Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs | Kang, Seokhyeong; Kahng, AB; Kumar, R; Sartori, J | CONFERENCE | 118 |
| 2013-10 | Enhancing the Efficiency of Energy-Constrained DVFS Designs | Kahng, Andrew B.; Kang, Seokhyeong; Kumar, Rakesh; Sartori, John | ARTICLE | 793 |
| 2018-03-19 | Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study | Kim, Seungwon; Han, Ki Jin; Kim, Youngmin; Kang, Seokhyeong | CONFERENCE | 129 |
| 2017-06-20 | Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization | Kim, Seungwon; Do, SangGi; Kang, Seokhyeong | CONFERENCE | 170 |
