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Kang, Seokhyeong
System-on-Chip Design Lab
Research Interests
  • System-on-Chip, low power, computer-aided design, physical implementation

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Many-Core Token-Based Adaptive Power Gating

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Title
Many-Core Token-Based Adaptive Power Gating
Author
Kahng, Andrew B.Kang, SeokhyeongRosing, Tajana SimunicStrong, Richard
Keywords
Adaptive power gating; energy savings; low power design; many-core architecture
Issue Date
2013-08
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.32, no.8, pp.1288 - 1292
Abstract
Among power dissipation components, leakage power has become more dominant with each successive technology node. Leakage energy waste can be reduced by power gating. In this paper, we extend token-based adaptive power gating (TAP), a technique to power gate an actively executing core during memory accesses, to many-core Chip Multi-Processors (CMPs). TAP works by tracking every system memory request and its estimated time of arrival so that a core may power gate itself without performance or energy loss. Previous work on TAP [11] shows several benefits compared to earlier state-of-the-art techniques [10], including zero performance hit and 2.58 times average energy savings for out-of-order cores. We show that TAP can adapt to increasing memory contention by increasing power-gated time by 3.69 times compared to a low memory-pressure case. We also scale TAP to many-core architectures with a distributed wake-up controller that is capable of supporting staggered wake-ups and able to power gate each core for 99.07% of the time, achieved by a non-scalable centralized scheme
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DOI
10.1109/TCAD.2013.2257923
ISSN
0278-0070
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