Ternary full adder using multi-threshold voltage graphene barristors
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- Ternary full adder using multi-threshold voltage graphene barristors
- Heo, Sunwoo; Kim, Sunmean; Kim, Kiyung; Lee, Hyeji; Kim, So-Young; Kim, Yun Ji; Kim, Seong Mo; Lee, Ho-In; Lee, Segi; Kim, Kyung Rok; Kang, Seokhyeong; Lee, Byoung Hun
- Issue Date
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- IEEE ELECTRON DEVICE LETTERS, v.39, no.12, pp.1948 - 1951
- Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10-16 J, which is comparable with the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.
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