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A Systematic Removal of Minimum Implant Area Violations under Timing Constraint

Jeong, Eunsol , Park , Heechun , Kim, Taewhan

Conference Paper Issue Date2022-03-14 View17

Advances in Design and Test of Monolithic 3-D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Park , Heechun , Kim, Jinwoo , Murali, Gauthaman , Lee, Edward , Kim, Daehyun , Lim, Sung Kyu , Mukhopadhyay, Saibal , Chakrabarty, Krishnendu

Article Issue Date2020-08 View16

Allocation of Always-On State Retention Storage for Power Gated Circuits-Steady-State- Driven Approach File

Kim, Taewhan , Park , Heechun

Article Issue Date2021-03 View21

Architecture, Chip, and Package Co-design Flow for 2.5D Integration of Reusable IP Chiplets

Kim, Jinwoo , Park, Heechun , Lim, Sung Kyu

Conference Paper Issue Date2019-06-02 View14

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse File

Kim, Jinwoo , Murali, Gauthaman , Park, Heechun , Qin, Eric , Kwon, Hyoukjun , Chekuri, Venkata Chaitanya Krishna , Rahman, Nael Mizanur , Dasari, Nihar , Singh, Arvind , Lee, Minah , et al

Article Issue Date2020-11 View17

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Kim, Jinwoo , Park , Heechun , Ku, Bon Woong , Kannan, Sukeshwar , Chakrabarty, Krishnendu , Lim, Sung Kyu

Article Issue Date2022-01 View16

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs

Chaudhuri, Arjun , Park, Heechun , Lim, Sung Kyu

Conference Paper Issue Date2019-05-27 View14

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

Park , Heechun , Chang, Kyungjoon , Kim, Taewhan

Conference Paper Issue Date2021-10-06 View9

Chiplet Placement with Sequence Pair Based Tree and Branch-and-Bound Method Considering Chiplet Ordering

Jeon, Gang-Min , Park, Heechun

Conference Paper Issue Date2024-01-24 View18

Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems File

Murali, Gauthaman , Park , Heechun , Qin, Eric , Torun, Hakki Mert , Dolatsara, Majid Ahadi , Swaminathan, Madhavan , Krishna, Tushar , Lim, Sung Kyu

Article Issue Date2021-04 View10

Clock TSV Fault-Tolerant 한 3 차원 IC 설계를 위한 TSV 공유 알고리즘

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2012-06-27 View18

Comprehensive Physical Design Flow Incorporating 3D Connections for Monolithic 3D ICs File

Kim, Suwan , Park , Heechun

Article Issue Date2024-01 View24

Comprehensive Technique for Designing and Synthesizing TSV Fault-Tolerant 3D Clock Trees File

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2013-11-18 View7

Deep Learning Driven Pre-Route Arc Length Prediction Considering Routing Priority

Jo, HM , Park, Heechun

Conference Paper Issue Date2024-01-24 View12

Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC File

Park, Heechun , Kim, Jinwoo , Chekuri, Venkata Chaitanya Krishna , Dolatsara, Majid Ahadi , Nabeel, Mohammed , Bojesomo, Alabi , Patnaik, Satwik , Sinanoglu, Ozgur , Swaminathan, Madhavan , Mukhopadhyay, Saibal , et al

Article Issue Date2020-12 View12

Design Space Exploration of Power Delivery in Heterogeneous Integration

Torun, Hakki Mert , Park, Heechun , Lim, Sung Kyu , Swaminathan, Madhavan

Conference Paper Issue Date2019-03-25 View16

Design-Technology Co-Optimization for Standard Cell Pin Length Modulation

Yoon, Junghyun , Park, Heechun

Conference Paper Issue Date2024-01-24 View16

Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations

Yoon, Junghyun , Park, Heechun

Conference Paper Issue Date2024-04-03 View33

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool

Chang, Kyungjoon , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2023-04-17 View15

Eliminating Minimum Implant Area Violations With Design Quality Preservation File

Jeong, Eunsol , Kim, Taewhan , Park , Heechun

Article Issue Date2023-05 View16

Enabling Heterogeneous IP Reuse with Interposer-based 2.5D ICs and Custom Interface Protocol

Kim, Jinwoo , Park, Heechun , Lim, Sung Kyu

Conference Paper Issue Date2019-03-25 View7

Fault Coverage and Resource Analysis for Diverse Structures of Clock TSV Fault-Tolerant Units in 3D ICs

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2013-11-17 View1

Graph Neural Network-Based Detailed Placement Optimization Framework

Lim, Dho Ui , Park, Heechun

Conference Paper Issue Date2024-04-03 View43

Hybrid asynchronous circuit generation amenable to conventional EDA flow File

Park , Heechun , Kim, Taewhan

Article Issue Date2019-01 View16

Logic-in-Memory Technology Mapping Framework for Memristor Crossbar with Maximized Parallelism

Kim, Ik-Kyum , Park, Heechun

Conference Paper Issue Date2024-01-24 View14

Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement

Jeong, Eunsol , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2021-08-09 View10

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs

Park, Heechun , Ku, Bonwoong , Lim, Sung-kyu

Conference Paper Issue Date2020-09-20 View17

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements File

Park , Heechun , Ku, Bon Woong , Chang, Kyungwook , Shim, Da Eun , Lim, Sung Kyu

Article Issue Date2021-09 View16

RTL-to-GDS Design Tools for Monolithic 3D ICs Built with Carbon Nanotube Transistors and Resistive Memory

Kim, Jinwoo , Park, Heechun , Lim, Sung Kyu

Conference Paper Issue Date2020-03-16 View15

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs

Park, Heechun , Chang, Kyungwook , Lim, Sung Kyu

Conference Paper Issue Date2019-06-02 View15

Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis

Kim, Seyoung , Park , Heechun , Kim, Jaeha

Conference Paper Issue Date2021-10-06 View15

Speeding-up neuromorphic computation for neural networks: Structure optimization approach File

Park , Heechun , Kim, Taewhan

Article Issue Date2022-01 View15

Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Networks

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2018-03-19 View10

Synthesis of TSV Fault-Tolerant 3-D Clock Trees File

Park, Heechun , Kim, Taewhan

Article Issue Date2015-02 View15

Synthesizing Asynchronous Circuits Toward Practical Use File

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2016-07-11 View10

Tightly Linking 3D via Allocation towards Routing Optimization for Monolithic 3D ICs

Kim, Suwan , Chung, Sehyeon , Park , Heechun

Conference Paper Issue Date2022-08-01 View13

Timing-Aware Tier Partitioning for 3D ICs With Critical Path Consideration

Park, Sojung , Park , Heechun

Conference Paper Issue Date2024-01-28 View17

Timing-Aware Tier Partitioning for 3D ICs With Critical Path Consideration

Park, Sojung , Park, Heechun

Conference Paper Issue Date2024-01-24 View13

Unsupervised Learning-Based Legalization with Graph Neural Network

Lim, Dho Ui , Park, Heechun

Conference Paper Issue Date2024-01-24 View17

비동기식 회로 설계 구조에 대한 전력 및 면적 비교

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2015-11-27 View13

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