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Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems

Author(s)
Murali, GauthamanPark , HeechunQin, EricTorun, Hakki MertDolatsara, Majid AhadiSwaminathan, MadhavanKrishna, TusharLim, Sung Kyu
Issued Date
2021-04
DOI
10.1109/TVLSI.2021.3058300
URI
https://scholarworks.unist.ac.kr/handle/201301/81625
Citation
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.29, no.4, pp.605 - 616
Abstract
The 2-D CMOS process technology scaling may have reached its pinnacle, yet it is not feasible to manufacture all computing elements at lower technological nodes. This has opened a new branch of chip designing that allows chiplets on different technological nodes to be integrated into a single package using interposers, the passive interconnection mediums. However, establishing a high-frequency communication over an entirely passive layer is one of the significant design challenges of 2.5-D systems. In this article, we present a robust clocking architecture for a 2.5-D system consisting of 64 processor cores. This clocking scheme consists of two major components, namely, interposer clocking and on-chiplet clocking. The interposer clocking consists of clocks used to achieve global synchronicity and clocks for interchiplet communication established using the AIB protocol. We synthesized these clocking components using commercial EDA tools and analyzed them using standard tools, on-chip, and package models. We also compare these results against a 2-D design of the same benchmark and another 2.5-D clocking architecture. Our experiments show that the absolute clock power is up to 16% less, and the ratio of clock power to system power is up to 4% less in the 2.5-D design than its 2-D counterpart.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
1063-8210
Keyword (Author)
ClocksDegradationRouting protocolsRoutingCrosstalkSiliconMetals25-D clockingclock metricsheterogeneous systemshierarchical clockingRISC-V architecture

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