Eliminating Minimum Implant Area Violations With Design Quality Preservation

Abstract

Minimum implant area (MIA) violation has emerged in the sub-micrometer technology which requires a certain amount of threshold voltage (Vt) area for the fab-rication. Elimination of MIA violations in the sign-off lay-out thus becomes an inevitable task for a high-performance multiple-Vt design. Conventional approaches as well as the previous efforts to remove MIA violations bring severe defects to the final design in that locally moving cells or reassigning Vts make the timing constraints unsatisfied or power consumption to be exploded. In this article, we propose a comprehensive MIA violation removal algorithm that fully and systematically controls the timing budget and power overhead with three sequential steps: 1) removing intra-row MIA violations by Vt reassignment under timing preservation and minimal power increments; 2) removing inter-row MIA violations with a theoretically optimal Vt reassignment while satisfying timing constraints; and 3) refining Vt reassignment to recover the power loss without violating both MIA constraints and timing closure. Moreover, we introduce a preprocessing algorithm at the preroute stage to remove a huge amount of MIA violations in advance for an additional runtime reduction without design quality degradation. Experiments through benchmark circuits show that our proposed approach completely resolve MIA violations while ensuring no timing violation and using 34.6% less power overhead on average than the conventional approaches and previous works. In addition, our preprocessing step reduces 45%-88% of MIA violations before the routing stage, which incurs 41% faster MIA removal on average in the final stage with similar design quality.