| 2017-05-22 | A Novel Ternary Multiplier based on Ternary CMOS Compact Model | Kang, Yesung; Kim, Jaewoo; Kim, Sunmin; Shin, Sunhae; Jang, E-San; Jeong, Jae Won; Kim, Kyung Rok; Kang, Seokhyeong | CONFERENCE | 59 |
| 2017-05-22 | CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits | Shin, Sunhae; Jang, Esan; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 40 |
| 2018-02-05 | Common Body for Ternary CMOS Logic Gates for Endurance of the Input Pattern Effects on Intermediate State Level | Jang, Esan; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 36 |
| 2016-02-23 | Compact CMOS-based multi-valued literal gate as a building block for multi valued logic and memory applications | Jang, E-San; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 37 |
| 2015-08 | Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology | Shin, Sunhae; Jang, Esan; Jeong, Jae Won; Park, Byung-Gook; Kim, Kyung Rok | ARTICLE | 838 |
| 2017-02-14 | Demonstration of CMOS with Gate-Bias Independent Junction Band-to-Band Tunneling Current for Standard Ternary Inverter | Sunhae Shin; Jang, Esan; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 24 |
| 2016-06-12 | Demonstration of standrad ternary inverter based on CMOS technology | Shin, Sunhae; Jang, Esan; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 52 |
| 2019-02-13 | Experimental Demonstration of Ternary CMOS with Variation of Process Based on Ion Implantation | Jeong, Jae Won; Choi, Young Eun; Kim, Woo Seok; Kim, Kyung Rok | CONFERENCE | 34 |
| 2019-06-27 | Experimental Demonstration of Ternary CMOS with Variation of Process Based on Ion Implantation | Jeong, Jae Won; Choi, Young Eun; Kim, Woo Seok; Kim, Kyung Rok | CONFERENCE | 35 |
| 2017-07-03 | Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-k Spacer Technology | Jang, E-San; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 107 |
| 2018-06 | Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-kappa Spacer Technology | Jang, Esan; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung Rok | ARTICLE | 336 |
| 2017-02-14 | Low leakage III-V/Ge CMOS FinFET design with high-k spacer technology | Jang, E-San; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 30 |
| 2015-02-11 | Multiple Negative Differential Resistance Device by Using the Ambipolar Behavior of TFET with Fast Switching Characteristics | Jeong, Jae Won; Shin, Sunhae; Jang, E-san; Kim, Kyung Rok | CONFERENCE | 43 |
| 2016-05 | Multiple Negative Differential Resistance Device by Using the Ambipolar Behavior of Tunneling Field Effect Transistor with Fast Switching Characteristics | Jeong, Jae Won; Jang, E-San; Shin, Sunhae; Kim, Kyung Rok | ARTICLE | 1798 |
| 2012-03 | Self-Assembly-Induced Formation of High-Density Silicon Oxide Memristor Nanostructures on Graphene and Metal Electrodes | Park, Woon Ik; Yoon, Jong Moon; Park, Moonkyu; Lee, Jinsup; Kim, Sung Kyu; Jeong, Jae Won; Kim, Kyungho; Jeong, Hu Young; Jeon, Seokwoo; No, Kwang Soo; Lee, Jeong Yong; Jung, Yeon Sik | ARTICLE | 718 |
| 2019-07 | Tunnelling-based ternary metal–oxide–semiconductor technology | Jeong, Jae Won; Choi, Young Eun; Kim, Woo Seok; Park, Jee-Ho; Kim, Sunmean; Shin, Sunhae; Lee, Kyuho; Chang, Jiwon; Kim, Seong-Jin; Kim, Kyung Rok | ARTICLE | 1079 |
| 2017-07-26 | Ultra-Low Standby Power and Static Noise-Immune Standard Ternary Inverter Based on Nanoscale Ternary CMOS Technology | Shin, Sunhae; Jeong, Jae Won; Jang, Esan; Kim, Kyung Rok | CONFERENCE | 107 |
| 2019-04 | ZnO composite nanolayer with mobility edge quantization for multi-value logic transistors | Lee, Lynn; Hwang, Jeongwoon; Jung, Jin Won; Kim, Jongchan; Lee, Ho-In; Heo, Sunwoo; Yoon, Minho; Choi, Sungju; Van Long, Nguyen; Park, Jinseon; Jeong, Jae Won; Kim, Jiyoung; Kim, Kyung Rok; Kim, Dae Hwan; Im, Seongil; Lee, Byoung Hun; Cho, Kyeongjae; Sung, Myung Mo | ARTICLE | 267 |
