Ternary Metal-Oxide-Semiconductor Technology and Design for Neuromorphic Processing-in-Memory Architecture

Abstract

The power and information density limits faced by a complementary metal-oxide-semiconductor (CMOS) technology could be solved by shifting from a binary to a ternary system, but no reports have detailed power-scalable and mass-producible ternary device platforms. The proposed approach based on single threshold voltage (VT) scheme, which employs the additional third voltage state implemented by exploiting the sub-VT off-state level constant current that is achieved by band-to-band tunneling (BTBT), enables both of the static power and dynamic power to be significantly scaled down.

For the first time, Ternary CMOS (T-CMOS) has been demonstrated successfully on large-scale 8-inch wafer using conventional CMOS 130-/90-nm process foundries with ternary logic and memory circuit operation. The constant current can be reduced to sub-picoampere level even at scaled operating voltage (VDD) = 0.5 V. The third half-VDD state in the ternary inverter based on T-CMOS exhibits a remarkably small standard deviation of 16 mV at VDD = 1 V for the 2 ~ 3 times variations of the BTBT currents. The variation-tolerant and symmetric in-out voltage-transfer characteristics enable us to demonstrate the T-CMOS integrated circuits including the ternary latch cell for trit-based logic and memory functions.

From the experimental results, it could be expected that adopting advanced technology node including 3D structure design or Steep-Slope characteristics of transistors such as tunnel FETs (TFETs) could substantially enhance the scalability of T-CMOS technology, allowing mega-hertz level high performance ternary application. Through 12-inch (300 mm) wafer measurements, which was processed by 28-nm foundry process, off-leakage variation was confirmed still within one order-of-mags even for minimum device size (L= 30nm, W= 80nm) and thus, the remarkable variation-tolerance of the intermediate ternary state is expected at VDD < 0.5 V as well as improved scalability of T-CMOS by lower thermal budget. The future-oriented T-CMOS design approach is quantitatively explored for achieving formidable scalability for several technology nodes from 130-nm to 2-nm.

The first demonstration of TritCellTM operation was performed by the T-Latch based on the T-CMOS with L/W= 130/400nm. the successful TritCellTM operation has been obtained with pre-charged VBL= VBLB = VDD= 0.7 V. In terms of delay and operation frequency, the measured TritCellTM delays for each data transition are more than 1000 times smaller than the sequential logic delays expected from static current level. Furthermore, issue analysis of TritCellTM operation was performed for optimized design by considering array size limitation. Proposed device Tristor, implemented by combining CFET with TFET concept and ultra-high density TritCellTM on 3D-stacked two Tristors enable extremely high scalability to be realized with achieving considerable area efficiency. The functionality of TritCellTM with T-IMC circuit and PIM architecture with ternary weight cell provide a promising route for ultimately energy-efficient, algorithm-friendly AI hardware with ternary PIM that is applicable very broad application area.