Scholarworks@UNIST

UNIST Library
Search

박희천
Park, Heechun

박희천

전기전자공학과

Researcher ID Research Gate ORCiD Scopus Google Scholar
Previous
Advances and Future Challenges in Monolithic 3D Integrated Logic, Power, and Optoelectronics Technologies for Tightly Interconnected Intelligent Systems File

Jung, Haksoon , Choi, Joonghoon , Baek, Seunghun , Shin, Bong Gyu , Song, Young Jae , Jung, Hanggyo , Kim, JoHyeon , Jeon, Jongwook , Kim, Gyumin , Park, Heechun , et al

Article Issue Date2026-03 View51
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement File

Ahn, Jaehoon , Chang, Kyungjoon , Choi, Kyu-Myung , Kim, Taewhan , Park, Heechun

Article Issue Date2024-08 View113
Comprehensive Physical Design Flow Incorporating 3D Connections for Monolithic 3D ICs File

Kim, Suwan , Park , Heechun

Article Issue Date2024-07 View125
Eliminating Minimum Implant Area Violations With Design Quality Preservation File

Jeong, Eunsol , Kim, Taewhan , Park , Heechun

Article Issue Date2023-05 View115
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Kim, Jinwoo , Park , Heechun , Ku, Bon Woong , Kannan, Sukeshwar , Chakrabarty, Krishnendu , Lim, Sung Kyu

Article Issue Date2022-01 View112
Speeding-up neuromorphic computation for neural networks: Structure optimization approach File

Park , Heechun , Kim, Taewhan

Article Issue Date2022-01 View135
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements File

Park , Heechun , Ku, Bon Woong , Chang, Kyungwook , Shim, Da Eun , Lim, Sung Kyu

Article Issue Date2021-09 View106
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems File

Murali, Gauthaman , Park , Heechun , Qin, Eric , Torun, Hakki Mert , Dolatsara, Majid Ahadi , Swaminathan, Madhavan , Krishna, Tushar , Lim, Sung Kyu

Article Issue Date2021-04 View91
Allocation of Always-On State Retention Storage for Power Gated Circuits-Steady-State- Driven Approach File

Kim, Taewhan , Park , Heechun

Article Issue Date2021-03 View115
Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC File

Park, Heechun , Kim, Jinwoo , Chekuri, Venkata Chaitanya Krishna , Dolatsara, Majid Ahadi , Nabeel, Mohammed , Bojesomo, Alabi , Patnaik, Satwik , Sinanoglu, Ozgur , Swaminathan, Madhavan , Mukhopadhyay, Saibal , et al

Article Issue Date2020-12 View96
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse File

Kim, Jinwoo , Murali, Gauthaman , Park, Heechun , Qin, Eric , Kwon, Hyoukjun , Chekuri, Venkata Chaitanya Krishna , Rahman, Nael Mizanur , Dasari, Nihar , Singh, Arvind , Lee, Minah , et al

Article Issue Date2020-11 View119
Advances in Design and Test of Monolithic 3-D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Park , Heechun , Kim, Jinwoo , Murali, Gauthaman , Lee, Edward , Kim, Daehyun , Lim, Sung Kyu , Mukhopadhyay, Saibal , Chakrabarty, Krishnendu

Article Issue Date2020-08 View103
Hybrid asynchronous circuit generation amenable to conventional EDA flow File

Park , Heechun , Kim, Taewhan

Article Issue Date2019-01 View107
Synthesis of TSV Fault-Tolerant 3-D Clock Trees File

Park, Heechun , Kim, Taewhan

Article Issue Date2015-02 View100
1

RSS 1.0 RSS 2.0

CONTACT US

UNIST | Library

Tel : 052-217-1403 / Email : scholarworks@unist.ac.kr

Copyright (c) 2023 by UNIST LIBRARY. All rights reserved.

ScholarWorks@UNIST was established as an OAK Project for the National Library of Korea.