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Park, Heechun

박희천

전기전자공학과

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Advances and Future Challenges in Monolithic 3D Integrated Logic, Power, and Optoelectronics Technologies for Tightly Interconnected Intelligent Systems File

Jung, Haksoon , Choi, Joonghoon , Baek, Seunghun , Shin, Bong Gyu , Song, Young Jae , Jung, Hanggyo , Kim, JoHyeon , Jeon, Jongwook , Kim, Gyumin , Park, Heechun , et al

Article Issue Date2026-03 View13
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement File

Ahn, Jaehoon , Chang, Kyungjoon , Choi, Kyu-Myung , Kim, Taewhan , Park, Heechun

Article Issue Date2024-08 View103
Comprehensive Physical Design Flow Incorporating 3D Connections for Monolithic 3D ICs File

Kim, Suwan , Park , Heechun

Article Issue Date2024-07 View121
Eliminating Minimum Implant Area Violations With Design Quality Preservation File

Jeong, Eunsol , Kim, Taewhan , Park , Heechun

Article Issue Date2023-05 View104
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Kim, Jinwoo , Park , Heechun , Ku, Bon Woong , Kannan, Sukeshwar , Chakrabarty, Krishnendu , Lim, Sung Kyu

Article Issue Date2022-01 View101
Speeding-up neuromorphic computation for neural networks: Structure optimization approach File

Park , Heechun , Kim, Taewhan

Article Issue Date2022-01 View97
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements File

Park , Heechun , Ku, Bon Woong , Chang, Kyungwook , Shim, Da Eun , Lim, Sung Kyu

Article Issue Date2021-09 View100
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems File

Murali, Gauthaman , Park , Heechun , Qin, Eric , Torun, Hakki Mert , Dolatsara, Majid Ahadi , Swaminathan, Madhavan , Krishna, Tushar , Lim, Sung Kyu

Article Issue Date2021-04 View85
Allocation of Always-On State Retention Storage for Power Gated Circuits-Steady-State- Driven Approach File

Kim, Taewhan , Park , Heechun

Article Issue Date2021-03 View109
Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC File

Park, Heechun , Kim, Jinwoo , Chekuri, Venkata Chaitanya Krishna , Dolatsara, Majid Ahadi , Nabeel, Mohammed , Bojesomo, Alabi , Patnaik, Satwik , Sinanoglu, Ozgur , Swaminathan, Madhavan , Mukhopadhyay, Saibal , et al

Article Issue Date2020-12 View92
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse File

Kim, Jinwoo , Murali, Gauthaman , Park, Heechun , Qin, Eric , Kwon, Hyoukjun , Chekuri, Venkata Chaitanya Krishna , Rahman, Nael Mizanur , Dasari, Nihar , Singh, Arvind , Lee, Minah , et al

Article Issue Date2020-11 View109
Advances in Design and Test of Monolithic 3-D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Park , Heechun , Kim, Jinwoo , Murali, Gauthaman , Lee, Edward , Kim, Daehyun , Lim, Sung Kyu , Mukhopadhyay, Saibal , Chakrabarty, Krishnendu

Article Issue Date2020-08 View98
Hybrid asynchronous circuit generation amenable to conventional EDA flow File

Park , Heechun , Kim, Taewhan

Article Issue Date2019-01 View104
Synthesis of TSV Fault-Tolerant 3-D Clock Trees File

Park, Heechun , Kim, Taewhan

Article Issue Date2015-02 View96
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