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박희천
Park, Heechun

박희천

Department of Electrical Engineering(전기전자공학과)

Researcher ID Research Gate ORCiD Scopus Google Scholar
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DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement File

Ahn, Jaehoon , Chang, Kyungjoon , Choi, Kyu-Myung , Kim, Taewhan , Park, Heechun

Article Issue Date2024-08 View26
Comprehensive Physical Design Flow Incorporating 3D Connections for Monolithic 3D ICs File

Kim, Suwan , Park , Heechun

Article Issue Date2024-07 View49
Eliminating Minimum Implant Area Violations With Design Quality Preservation File

Jeong, Eunsol , Kim, Taewhan , Park , Heechun

Article Issue Date2023-05 View32
Speeding-up neuromorphic computation for neural networks: Structure optimization approach File

Park , Heechun , Kim, Taewhan

Article Issue Date2022-01 View25
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Kim, Jinwoo , Park , Heechun , Ku, Bon Woong , Kannan, Sukeshwar , Chakrabarty, Krishnendu , Lim, Sung Kyu

Article Issue Date2022-01 View29
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements File

Park , Heechun , Ku, Bon Woong , Chang, Kyungwook , Shim, Da Eun , Lim, Sung Kyu

Article Issue Date2021-09 View38
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems File

Murali, Gauthaman , Park , Heechun , Qin, Eric , Torun, Hakki Mert , Dolatsara, Majid Ahadi , Swaminathan, Madhavan , Krishna, Tushar , Lim, Sung Kyu

Article Issue Date2021-04 View23
Allocation of Always-On State Retention Storage for Power Gated Circuits-Steady-State- Driven Approach File

Kim, Taewhan , Park , Heechun

Article Issue Date2021-03 View29
Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC File

Park, Heechun , Kim, Jinwoo , Chekuri, Venkata Chaitanya Krishna , Dolatsara, Majid Ahadi , Nabeel, Mohammed , Bojesomo, Alabi , Patnaik, Satwik , Sinanoglu, Ozgur , Swaminathan, Madhavan , Mukhopadhyay, Saibal , et al

Article Issue Date2020-12 View29
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse File

Kim, Jinwoo , Murali, Gauthaman , Park, Heechun , Qin, Eric , Kwon, Hyoukjun , Chekuri, Venkata Chaitanya Krishna , Rahman, Nael Mizanur , Dasari, Nihar , Singh, Arvind , Lee, Minah , et al

Article Issue Date2020-11 View30
Advances in Design and Test of Monolithic 3-D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Park , Heechun , Kim, Jinwoo , Murali, Gauthaman , Lee, Edward , Kim, Daehyun , Lim, Sung Kyu , Mukhopadhyay, Saibal , Chakrabarty, Krishnendu

Article Issue Date2020-08 View27
Hybrid asynchronous circuit generation amenable to conventional EDA flow File

Park , Heechun , Kim, Taewhan

Article Issue Date2019-01 View25
Synthesis of TSV Fault-Tolerant 3-D Clock Trees File

Park, Heechun , Kim, Taewhan

Article Issue Date2015-02 View34
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