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Park, Heechun
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DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement

Author(s)
Ahn, JaehoonChang, KyungjoonChoi, Kyu-MyungKim, TaewhanPark, Heechun
Issued Date
2024-08
DOI
10.1109/TCAD.2024.3370110
URI
https://scholarworks.unist.ac.kr/handle/201301/84044
Citation
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.43, no.8, pp.2493 - 2506
Abstract
Deep learning (DL) models have recently paid considerable attention to timing prediction in the place-and-route (P&R) flow. As yet, the DL-based prior works are confined to timing prediction at the time-consuming routing stage, and very few have addressed the timing prediction problem at the placement, i.e., at the pre-route stage. Moreover, no work has addressed a seamless link of timing prediction at the pre-route stage to the final timing optimization through commercial P&R tools. In this work, we introduce a novel framework called DTOC-P that seamlessly integrates deep-learning-driven timing optimization into cutting-edge commercial P&R tools. Our framework is composed of two phases: 1) the pre-route timing prediction phase that performs DL-driven arc delay and arc output slew prediction with an elaborated hierarchical model and 2) the timing optimization phase which incorporates commercial P&R tools with DL-driven prediction outcomes to perform timing optimization. In addition, the DTOC-P framework achieves enhanced practicality with the application of continual learning in the timing prediction phase, and the concept of anomaly detection in the timing optimization phase. Experimental results show that our DTOC-P framework improves pre-route prediction accuracy by up to 55% and 47% on arc delay and arc output, which are further enhanced to encompass a broader range of designs by continual learning supported in DTOC-P, practically using a tenfold reduced training time compared to retraining all datasets from scratch. In terms of timing optimization, our experiments reveal that the DTOC-P framework improves WNS, TNS, and the number of timing violation paths by up to 12%, 41%, and 34%, respectively, which is a remarkable progress compared to its predecessor through the integration of anomaly detection that excludes potential outliers to effectively protect against erroneous timing updates during the timing optimization phase.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
0278-0070
Keyword (Author)
OptimizationTrainingRoutingPinsLogic gatesFeature extractionAnomaly detectioncontinual learningdelay predictionmachine learning for CADtiming optimizationDelays

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