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153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier File

Choi, Seojin , Yoo, Seyeon , Lee, Yongsun , Jo, Yongwoo , Lee, Jeonghyun , Lim, Younghyun , Choi, Jaehyouk

Conference Paper Issue Date2018-06-20 View45
A -242-dB FOM and -71-dBc Reference Spur Ring-VCO-Based Ultra-Low Jitter Switched-Loop-Filter PLL Using Fast Phase-Error Correction Technique File

Seong, Taeho , Lee, Yongsun , Yoo, Seyeon , Choi, Jaehyouk

Conference Paper Issue Date2017-06-07 View64
A 140fs rms -Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator File

Yoo, Seyeon , Choi, Seojin , Lee, Yongsun , Seong, Taeho , Lim, Younghyun , Choi, Jaehyouk

Conference Paper Issue Date2019-02-17 View77
A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC File

Seong, Taeho , Lee, Yongsun , Yoo, Seyeon , Choi, Jaehyouk

Article Issue Date2019-09 View63
A 320μV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector File

Lim, Younghyun , Lee, Jeonghyun , Lee, Yongsun , Yoo, Seyeon , Choi, Jaehyouk

Conference Paper Issue Date2018-09-03 View42
A 76fs rms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization File

Kim, Juyeop , Yoon, Heein , Lim, Younghyun , Lee, Yongsun , Cho, Yoonseo , Seong, Taeho , Choi, Jaehyouk

Conference Paper Issue Date2019-02-17 View87
A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier with a Two-Phase PVT-Calibrator for ΔΣ PLLs File

Lee, Yongsun , Kim, Mina , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2015-03 View75
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers File

Yoo, Seyeon , Choi, Seojin , Kim, Juyeop , Yoon, Heein , Lee, Yongsun , Choi, Jaehyouk

Article Issue Date2018-02 View72
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M File

Hwang, Chanwoong , Park, Hangi , Lee, Yongsun , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2022-09 View52
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator File

Yoo, Seyeon , Choi, Seojin , Lee, Yongsun , Seong, Taeho , Lim, Younghyun , Choi, Jaehyouk

Article Issue Date2021-01 View55
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique File

Lee, Yongsun , Seong, Taeho , Yoo, Seyeon , Choi, Jaehyouk

Article Issue Date2018-04 View59
A PVT-Robust -39dBc 1kHz-to-100MHz Integrated-Phase-Noise 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop Using the Averages of Phase Deviations for mm-Band 5G Transceivers File

Yoo, Seyeon , Choi, Seojin , Kim, Juyeop , Yoon, Heein , Lee, Yongsun , Choi, Jaehyouk

Conference Paper Issue Date2017-02-08 View62
A PVT-Robust Low Reference Spur Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop File

Lee, Yongsun , Yoon, Heein , Choi, Jaehyouk

Conference Paper Issue Date2016-06-15 View62
A switched-loop-filter PLL with fast phase-error correction technique File

Lee, Yongsun , Seong, Taeho , Yoo, Seyeon , Choi, Jaehyouk

Conference Paper Issue Date2018-01-22 View54
A wideband dual-mode LC-VCO with a switchable gate-biased active core File

Yoon, Heein , Lee, Yongsun , Kim, Jae Joon , Choi, Jaehyouk

Article Issue Date2014-05 View87
A −242dB FOM and −75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC File

Seong, Taeho , Lee, Yongsun , Yoo, Seyeon , Choi, Jaehyouk

Conference Paper Issue Date2018-02-14 View69
A −31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers File

Yoon, Heein , Kim, Juyeop , Park, Suneui , Lim, Younghyun , Lee, Yongsun , Bang, Jooeun , Lim, Kyoohyun , Choi, Jaehyouk

Conference Paper Issue Date2018-02-14 View53
A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word File

Seong, Taeho , Lee, Yongsun , Hwang, Chanwoong , Lee, Jeonghyun , Park, Hangi , Lee, Kyuho Jason , Choi, Jaehyouk

Conference Paper Issue Date2020-02-18 View90
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current File

Lim, Younghyun , Lee, Jeonghyun , Lee, Yongsun , Song, Seong-Sik , Kim, Hong-Teuk , Lee, Ockgoo , Choi, Jaehyouk

Article Issue Date2017-11 View49
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114 File

Choi, Seojin , Yoo, Seyeon , Lee, Yongsun , Jo, Yongwoo , Lee, Jeongyun , Lim, Younghyun , Choi, Jaehyouk

Article Issue Date2019-04 View62
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators File

Kim, Juyeop , Lim, Younghyun , Yoon, Heein , Lee, Yongsun , Park, Hangi , Cho, Yoonseo , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2019-12 View90
Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers File

Yoo, Seyeon , Choi, Seojin , Kim, Juyeop , Yoon, Heein , Lee, Yongsun , Choi, Jaehyouk

Conference Paper Issue Date2018-01-22 View75
LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS File

Lee, Yongsun

Thesis Issue Date2020-02 View52
Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration File

Seong, Taeho , Lee, Yongsun , Choi, Jaehyouk

Article Issue Date2014-09 View93
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