A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier with a Two-Phase PVT-Calibrator for ΔΣ PLLs
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- A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier with a Two-Phase PVT-Calibrator for ΔΣ PLLs
- Lee, Yongsun; Kim, Mina; Seong, Taeho; Choi, Jaehyouk
- Issue Date
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.3, pp.635 - 644
- A low phase noise injection-locked reference clock multiplier that can suppress the delta-sigma $(DeltaSigma)$ noise of $DeltaSigma$ phase-locked loops (PLLs) is proposed. By adopting a two-phase PVT-calibrator that switches the calibration resolution, the clock multiplier can reduce the frequency-acquisition time, as well as tightly regulate the real-time degradation of the phase noise. To improve the performance of the calibration method utilizing two identical oscillators, the self-injection pulse generator that balances the loadings of two oscillators is proposed. In addition, this work presents a systematic design methodology that minimizes the degradation of the phase noise over the PVT variations, based on the phase noise analysis of injection-locking. The clock multiplier was designed with the prototype $DeltaSigma$ PLL in the 65-nm CMOS process. It can provide five reference frequencies, i.e., 19.2, 28.8, 48, 57.6, and 96 MHz. The phase noise of the 96-MHz signal was $-$130.0 and $-$131.8 dBc/Hz at 100 kHz and 1 MHz offsets, respectively; the performance of low phase noise was confirmed over temperature variations. The total active area was 0.062 mm2, and the power consumption was 1.6-1.9 mW. By switching the reference frequency from 19.2 to 96 MHz, the phase noise of the prototype PLL at the 10-MHz offset from the 4.4-GHz signal was improved from $-$120.1 to $-$138.6 dBc/Hz.
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