A -242-dB FOM and -71-dBc Reference Spur Ring-VCO-Based Ultra-Low Jitter Switched-Loop-Filter PLL Using Fast Phase-Error Correction Technique

Abstract

This work presents an ultra-low jitter and low reference spur switched-loop-filter (SLF) PLL, using a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). Thus, despite a high multiplication factor (i.e., 64), the proposed SLF-PLL achieved ultra-low jitter and low reference spur, concurrently. From the prototype fabricated using a 65-nm CMOS process, the RMS-jitter, the FOM, and the reference spur were measured as 378 fs, −242 dB, and −71 dBc, respectively.