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Choi, Jaehyouk
Integrated Circuits and Systems Lab (ICSL)
Research Interests
  • RF/Analog/Mixed IC design, low power CMOS IC, wired/wireless TRX IC, clock generation IC

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Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration

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Title
Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration
Author
Seong, TaehoLee, YongsunChoi, Jaehyouk
Issue Date
2014-09
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.61, no.9, pp.701 - 705
Abstract
oraclA new design methodology is proposed for an ultralow in-band phase noise injection-locked frequency multiplier (ILFM) based on open-loop frequency calibration. The prototype ILFM was designed and fabricated in the 65-nm CMOS process. Using an open-loop calibrator without a real-time monitoring loop, the ILFM achieved excellent in-band phase noise with low power consumption and a small silicon area. Following the design procedure based on the phase noise analysis, the proposed ILFM showed that the open-loop calibrator was capable of overcoming phase noise degradation due to process-voltage-temperature variations. The output frequency was 3.0 GHz when the oscillator was injection locked by the 15th harmonic of the 200-MHz reference clock. The in-band phase noise performance was -117.0, -122.6, and -124.5 dBc/Hz at 10-, 100-, and 1-MHz offsets, respectively. The total active area was 0.19 mm(2), and the power consumption was 8.1 mW.
URI
https://scholarworks.unist.ac.kr/handle/201301/7102
DOI
10.1109/TCSII.2014.2335435
ISSN
1549-7747
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