A switched-loop-filter PLL with fast phase-error correction technique

Abstract

A low-jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction (FPEC) technique emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM) is presented. Even for a high multiplication factor (i.e., 64), the proposed SLF PLL concurrently achieved ultra-low jitter and low reference spur. The prototype was fabricated in a 65-nm CMOS process. The RMS-jitter, the FOM, and the reference spur were measured as 378 fs, -242 dB, and -71 dBc, respectively.