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A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits File

Kim, Sunmean , Lee, Sung-Yun , Park, Sunghye , Kim, Kyung Rok , Kang, Seokhyeong

Article Issue Date2020-09 View5

A Metaheuristic Method for Fast Multi-Deck Legalization File

Do, SangGi

Thesis Issue Date2018-02 View10

A New Methodology for Reduced Cost of Resilience File

Kang, Seokhyeong , Kahng, Andrew B. , Li, Jiajia

Conference Paper Issue Date2014-05-22 View16

A novel design methodology for error-resilient circuits in near-Threshold computing File

Lee, Jaemin , Kim, Sunmean , Kim, Youngmin , Kang, Seokhyeong

Conference Paper Issue Date2016-10-26 View2

A Novel Methodology for Error-Resilient Circuits in Near-Threshold Computing File

Lee, Jaemin

Thesis Issue Date2017-08 View10

A Novel Ternary Multiplier based on Ternary CMOS Compact Model File

Kang, Yesung , Kim, Jaewoo , Kim, Sunmin , Shin, Sunhae , Jang, E-San , Jeong, Jae Won , Kim, Kyung Rok , Kang, Seokhyeong

Conference Paper Issue Date2017-05-22 View5

A preliminary analysis of domain coupling in package power distribution network File

Bae, Byoungjin , Kim, Seungwon , Kim, Youngmin , Kang, Seokhyeong , Kim, Il Joon , Kim, Kwangseok , Kang, Sunwon , Han, Ki Jin

Conference Paper Issue Date2017-08-30 View4

Accuracy-Configurable Adder for Approximate Arithmetic Designs File

Kahng, Andrew B. , Kang, Seokhyeong

Conference Paper Issue Date2012-06-05 View5

Active-Mode Leakage Reduction with Data-Retained Power Gating File

Kahng, Andrew B. , Kang, Seokhyeong , Park, Bongil

Conference Paper Issue Date2013-03-18 View4

An Improved Methodology for Resilient Design Implementation File

Kahng, Andrew B. , Kang, Seokhyeong , Li, Jiajia , De Gyvez, Jose Pineda

Article Issue Date2015-09 View5

An optimal gate design for the synthesis of ternary logic circuits File

Kim, Sunmean , Lim, Taeho , Kang, Seokhyeong

Conference Paper Issue Date2018-01-22 View3

An Optimal Gate Design for the Synthesis of Ternary Logic Circuits File

Kim, Sunmean

Thesis Issue Date2018-02 View8

An optimal operating point by using error monitoring circuits with an error-resilient technique File

Lee, Jaemin , Kim, Seungwon , Kim, Youngmin , Kang, Seokhyeong

Conference Paper Issue Date2015-10-05 View4

Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV models File

Kim, Seungwon , Han, Ki Jin , Kang, Seokhyeong , Kim, Youngmin

Conference Paper Issue Date2014-11-05 View4

Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions File

Kang, Seokhyeong , Kahng, Andrew B.

Conference Paper Issue Date2012-03-25 View2

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic File

Kim, Sunmean , Lee, Sung-Yun , Park, Sunghye , Kang, Seokhyeong

Conference Paper Issue Date2019-05-21 View4

Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs

Kang, Seokhyeong , Kahng, AB , Kumar, R , Sartori, J

Conference Paper Issue Date2010-01-10 View3

Enhancing the Efficiency of Energy-Constrained DVFS Designs File

Kahng, Andrew B. , Kang, Seokhyeong , Kumar, Rakesh , Sartori, John

Article Issue Date2013-10 View4

Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study File

Kim, Seungwon , Han, Ki Jin , Kim, Youngmin , Kang, Seokhyeong

Conference Paper Issue Date2018-03-19 View4

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization File

Kim, Seungwon , Do, SangGi , Kang, Seokhyeong

Conference Paper Issue Date2017-06-20 View1

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