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Showing results 3 to 16 of 16

CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits File

Shin, Sunhae , Jang, Esan , Jeong, Jae Won , Kim, Kyung Rok

Conference Paper Issue Date2017-05-22 View13
Common Body for Ternary CMOS Logic Gates for Endurance of the Input Pattern Effects on Intermediate State Level

Jang, Esan , Shin, Sunhae , Jeong, Jae Won , Kim, Kyung Rok

Conference Paper Issue Date2018-02-05 View47
Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology File

Shin, Sunhae , Jang, Esan , Jeong, Jae Won , Park, Byung-Gook , Kim, Kyung Rok

Article Issue Date2015-08 View20
Compact Model for Positive Gain-Embedded Voltage Transfer Curve of Inverter Based on Novel I-V Curves for Multi-Peak NDR

Jeong, Jaewon , Shin, Sunhae , Jang, Esan , Kim, Kyung Rok

Conference Paper Issue Date2017-02-15 View14
Demonstration of CMOS with Gate-Bias Independent Junction Band-to-Band Tunneling Current for Standard Ternary Inverter

Sunhae Shin , Jang, Esan , Jeong, Jae Won , Kim, Kyung Rok

Conference Paper Issue Date2017-02-14 View15
Demonstration of standrad ternary inverter based on CMOS technology File

Shin, Sunhae , Jang, Esan , Jeong, Jae Won , Kim, Kyung Rok

Conference Paper Issue Date2016-06-12 View19
Design of THz Aperture based on Near-Field Microscopy Technology for High Resolution THz Imaging

Jeon, Hyeong Ju , Ryu, Min Woo , Jang, Esan , Ahn, Sang Hyo , Kim, Kyung Rok

Conference Paper Issue Date2018-02-05 View22
Device optimization on gate oxide and spacer dielectric permittivity for 'well-tempered' nanoscale MOSFET File

Jang, Esan , Shin, Sunhae , Jung, Jae Won , Jung, Yu Jung , Kim, Kyung Rok

Conference Paper Issue Date2016-06-12 View15
Gate induced drain leakage reduction with analysis of gate fringing field effect on high-kappa/metal gate CMOS technology File

Jang, Esan , Shin, Sunhae , Jung, Jae Won , Kim, Kyung Rok

Article Issue Date2015-06 View22
Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-kappa Spacer Technology File

Jang, Esan , Shin, Sunhae , Jeong, Jae Won , Kim, Kyung Rok

Article Issue Date2018-06 View17
Multi-Valued Logic Based on CMOS technology

Kim, Kyung Rok , Shin, Sunhae , Jang, Esan , Jung, Jae Won

Conference Paper Issue Date2015-07-02 View19
Standard Ternary Inverter Based on Junction Leakage-Enhanced Nanoscale Planar CMOS and Its Variation Immunity File

Kim, Kyung Rok , Shin, Sunhae , Jang, Esan

Conference Paper Issue Date2014-06-08 View12
Tunnel FET-based negative differential resistance device with triple-peaks and ultra-high peak-to-valley current ratio

Jae Won Jeong , Shin, Sunhae , Jang, Esan , Kim, Kyung Rok

Conference Paper Issue Date2016-02-23 View13
Ultra-Low Standby Power and Static Noise-Immune Standard Ternary Inverter Based on Nanoscale Ternary CMOS Technology File

Shin, Sunhae , Jeong, Jae Won , Jang, Esan , Kim, Kyung Rok

Conference Paper Issue Date2017-07-26 View14
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