Active BSCDN Benchmark Framework with Backside-Compatible CNFET Logic Technology

Abstract

This study presents a benchmark framework for digital blocks featuring an active backside clock distribution network (BSCDN), which incorporates clock buffers and sinks implemented using backside-compatible logic based on carbon nanotube field-effect transistors (CNFETs). The proposed framework includes the fabrication, characterization and TCAD modeling of complementary CNFETs, neural network-based compact modeling, standard cell characterization, and a block-level benchmark comparing the performance of the active BSCDN with that of reported passive CDNs.