Scholarworks@UNIST

UNIST Library
Search

Browsing by Keyword : jitter

All A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
가 나 다 라 마 바 사 아 자 차 카 타 파 하
Sort by: In order: Results/Page Etal:

Showing results 1 to 12 of 12

A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC File

Seong, Taeho , Lee, Yongsun , Yoo, Seyeon , Choi, Jaehyouk

Article Issue Date2019-09 View167
A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-time PVT-Calibrator with Replica-Delay Cells File

Kim, Mina , Choi, Seojin , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2016-02 View156
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration File

Yoon, Heein , Park, Suneui , Choi, Jaehyouk

Article Issue Date2019-06 View115
A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector File

Choi, Seojin , Yoo, Seyeon , Lim, Younghyun , Choi, Jaehyouk

Article Issue Date2016-08 View163
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114 File

Choi, Seojin , Yoo, Seyeon , Lee, Yongsun , Jo, Yongwoo , Lee, Jeongyun , Lim, Younghyun , Choi, Jaehyouk

Article Issue Date2019-04 View107
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators File

Kim, Juyeop , Lim, Younghyun , Yoon, Heein , Lee, Yongsun , Park, Hangi , Cho, Yoonseo , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2019-12 View128
Analytical Calculation of Jitter Probability Density at Multistage Output Buffers Due to Supply Voltage Fluctuations File

Park, Eunkyeong , Kim, Hyungsoo , Shim, Jongjoo , Kim, Yong-Ju , Kim, Yun-Saing , Kim, Jingook

Article Issue Date2015-08 View150
Analytical Transfer Functions Relating Power and Ground Voltage Fluctuations to Jitter at a Single-Ended Full-Swing Buffer File

Hwang, Chulsoon , Kim, Jingook , Achkir, Brice , Fan, Jun

Article Issue Date2013-01 View106
Improved Target Impedance Concept With Jitter Specification File

Sun, Yin , Kim, Jingook , Ouyang, Muqi , Hwang, Chulsoon

Article Issue Date2020-08 View114
Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop File

Jeong, Myeongjo , Shin, Minchul , Kim, Jinwoo , Seung, Manho , Lee, Seokkiu , Kim, Jingook

Article Issue Date2020-10 View127
On-chip linear voltage regulator module (VRM) effect on power distribution network (PDN) noise and jitter at high-speed output buffer File

Kim, Heegon , Kim, Sukjin , Kim, Joungho , Yoon, Changwook , Achkir, Brice , Fan, Jun

Article Issue Date2015-08 View90
단방향 지연 변이와 일주 지연을 이용한 양단간의 단방향 지연 추정

김동근 , 이재용

Article Issue Date2008-01 View67
1

RSS 1.0 RSS 2.0

CONTACT US

UNIST | Library

Tel : 052-217-1403 / Email : scholarworks@unist.ac.kr

Copyright (c) 2023 by UNIST LIBRARY. All rights reserved.

ScholarWorks@UNIST was established as an OAK Project for the National Library of Korea.