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A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits File

Kim, Sunmean , Lee, Sung-Yun , Park, Sunghye , Kim, Kyung Rok , Kang, Seokhyeong

Article Issue Date2020-09 View53
A New Design Methodology for Ternary Circuits and Systems File File

Kim, Sunmean

Thesis Issue Date2021-02 View34
A novel design methodology for error-resilient circuits in near-Threshold computing File

Lee, Jaemin , Kim, Sunmean , Kim, Youngmin , Kang, Seokhyeong

Conference Paper Issue Date2016-10-26 View25
An optimal gate design for the synthesis of ternary logic circuits File

Kim, Sunmean , Lim, Taeho , Kang, Seokhyeong

Conference Paper Issue Date2018-01-22 View22
An Optimal Gate Design for the Synthesis of Ternary Logic Circuits File File

Kim, Sunmean

Thesis Issue Date2018-02 View20
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic File

Kim, Sunmean , Lee, Sung-Yun , Park, Sunghye , Kang, Seokhyeong

Conference Paper Issue Date2019-05-21 View30
Ternary full adder using multi-threshold voltage graphene barristors File File

Heo, Sunwoo , Kim, Sunmean , Kim, Kiyung , Lee, Hyeji , Kim, So-Young , Kim, Yun Ji , Kim, Seong Mo , Lee, Ho-In , Lee, Segi , Kim, Kyung Rok , et al

Article Issue Date2018-10 View106
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm File

Lee, Sung-Yun , Kim, Sunmean , Kang, Seokhyeong

Conference Paper Issue Date2019-05-21 View27
Tunnelling-based ternary metal–oxide–semiconductor technology File

Jeong, Jae Won , Choi, Young Eun , Kim, Woo Seok , Park, Jee-Ho , Kim, Sunmean , Shin, Sunhae , Lee, Kyuho , Chang, Jiwon , Kim, Seong-Jin , Kim, Kyung Rok

Article Issue Date2019-07 View94
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