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Showing results 4 to 13 of 13

Comprehensive Performance Analysis of Interconnect Variation by double and triple patterning lithography processes File

Kim, Youngmin , Lee, Jaemin , Ryu, Myunghwan

Article Issue Date2014-12 View31
Diffusion-rounded CMOS for improving both I-on and I-off characteristics File File

Ryu, Myunghwan , Nguyen, Hung Viet , Kim, Youngmin

Article Issue Date2011-11 View31
Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits File

Ryu, Myunghwan , Kim, Youngmin

Article Issue Date2015-08 View35
Junctionless Sandwiched-gate Logic Design using Novel Device Structure File

Ryu, Myunghwan , Kim, Youngmin

Article Issue Date2018-08 View12
On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor File File

Lee, Jaemin , Ryu, Myunghwan , Kim, Youngmin

Article Issue Date2015-06 View28
Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width File File

Ryu, Myunghwan , Bien, Franklin , Kim, Youngmin

Article Issue Date2016-01 View73
Process-induced Structural Variability-aware Performance Optimization for Advanced Nanoscale Technologies File File

Ryu, Myunghwan

Thesis Issue Date2016-08 View23
Sandwiched-Gate Inverter: Novel Device Structure for Future Logic Gates File

Ryu, Myunghwan , Bien, Franklin , Kim, Youngmin

Conference Paper Issue Date2015-09-09 View13
Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape File File

Ryu, Myunghwan , Kim, Youngmin

Article Issue Date2013-05 View26
TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC File

Nguyen, Hung Viet , Ryu, Myunghwan , Kim, Youngmin

Article Issue Date2012-12 View34
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