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Kim, Youngmin
Nano-scale(system) Design & Automation Lab
Research Interests
  • Design & Technology Co-Optimization (DTCO)
  • Variability-Aware and Robust Design Methodologies
  • Design for Manufacturability/Variability (DFM/V)
  • Low-Power and High Performance Circuit Design
  • 3D IC with TSV

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On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

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Title
On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor
Author
Lee, JaeminRyu, MyunghwanKim, Youngmin
Issue Date
2015-06
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v.12, no.12, pp.1 - 11
Abstract
Increasing short channel effects (SCEs) hinder further technology downscaling of CMOS transistors. Beyond the 10-nm technology node, the gate-all-around (GAA) FET is considered a promising solution for continuing Moore's law. In this study, we introduce a novel structure for speeding up the interconnect propagation using 10-nm channel length double gate-all around (DGAA) transistors. We propose a boosting structure that can significantly improve the performance of circuits by controlling the two gates of the DGAA independently. The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role in application-specific integration circuits in future GAA-based designs
URI
https://scholarworks.unist.ac.kr/handle/201301/16423
URL
https://www.jstage.jst.go.jp/article/elex/12/12/12_12.20150321/_article
DOI
10.1587/elex.12.20150321
ISSN
1349-2543
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EE_Journal Papers
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