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Kim, Youngmin
Nano-scale(system) Design & Automation Lab
Research Interests
  • Design & Technology Co-Optimization (DTCO)
  • Variability-Aware and Robust Design Methodologies
  • Design for Manufacturability/Variability (DFM/V)
  • Low-Power and High Performance Circuit Design
  • 3D IC with TSV

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Comprehensive Performance Analysis of Interconnect Variation by double and triple patterning lithography processes

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Title
Comprehensive Performance Analysis of Interconnect Variation by double and triple patterning lithography processes
Author
Kim, YoungminLee, JaeminRyu, Myunghwan
Issue Date
2014-12
Publisher
IEEK PUBLICATION CENTER
Citation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.14, no.6, pp.824 - 831
Abstract
In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.
URI
https://scholarworks.unist.ac.kr/handle/201301/9808
DOI
10.5573/JSTS.2014.14.6.824
ISSN
1598-1657
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