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A Systematic Removal of Minimum Implant Area Violations under Timing Constraint

Jeong, Eunsol , Park , Heechun , Kim, Taewhan

Conference Paper Issue Date2022-03-14 View17

Advances in Design and Test of Monolithic 3-D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Park , Heechun , Kim, Jinwoo , Murali, Gauthaman , Lee, Edward , Kim, Daehyun , Lim, Sung Kyu , Mukhopadhyay, Saibal , Chakrabarty, Krishnendu

Article Issue Date2020-08 View16

Allocation of Always-On State Retention Storage for Power Gated Circuits-Steady-State- Driven Approach File

Kim, Taewhan , Park , Heechun

Article Issue Date2021-03 View21

Architecture, Chip, and Package Co-design Flow for 2.5D Integration of Reusable IP Chiplets

Kim, Jinwoo , Park, Heechun , Lim, Sung Kyu

Conference Paper Issue Date2019-06-02 View14

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse File

Kim, Jinwoo , Murali, Gauthaman , Park, Heechun , Qin, Eric , Kwon, Hyoukjun , Chekuri, Venkata Chaitanya Krishna , Rahman, Nael Mizanur , Dasari, Nihar , Singh, Arvind , Lee, Minah , et al

Article Issue Date2020-11 View17

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs File

Chaudhuri, Arjun , Banerjee, Sanmitra , Kim, Jinwoo , Park , Heechun , Ku, Bon Woong , Kannan, Sukeshwar , Chakrabarty, Krishnendu , Lim, Sung Kyu

Article Issue Date2022-01 View16

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs

Chaudhuri, Arjun , Park, Heechun , Lim, Sung Kyu

Conference Paper Issue Date2019-05-27 View14

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

Park , Heechun , Chang, Kyungjoon , Kim, Taewhan

Conference Paper Issue Date2021-10-06 View9

Chiplet Placement with Sequence Pair Based Tree and Branch-and-Bound Method Considering Chiplet Ordering

Jeon, Gang-Min , Park, Heechun

Conference Paper Issue Date2024-01-24 View18

Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems File

Murali, Gauthaman , Park , Heechun , Qin, Eric , Torun, Hakki Mert , Dolatsara, Majid Ahadi , Swaminathan, Madhavan , Krishna, Tushar , Lim, Sung Kyu

Article Issue Date2021-04 View10

Clock TSV Fault-Tolerant 한 3 차원 IC 설계를 위한 TSV 공유 알고리즘

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2012-06-27 View18

Comprehensive Physical Design Flow Incorporating 3D Connections for Monolithic 3D ICs File

Kim, Suwan , Park , Heechun

Article Issue Date2024-01 View24

Comprehensive Technique for Designing and Synthesizing TSV Fault-Tolerant 3D Clock Trees File

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2013-11-18 View7

Deep Learning Driven Pre-Route Arc Length Prediction Considering Routing Priority

Jo, HM , Park, Heechun

Conference Paper Issue Date2024-01-24 View12

Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC File

Park, Heechun , Kim, Jinwoo , Chekuri, Venkata Chaitanya Krishna , Dolatsara, Majid Ahadi , Nabeel, Mohammed , Bojesomo, Alabi , Patnaik, Satwik , Sinanoglu, Ozgur , Swaminathan, Madhavan , Mukhopadhyay, Saibal , et al

Article Issue Date2020-12 View12

Design Space Exploration of Power Delivery in Heterogeneous Integration

Torun, Hakki Mert , Park, Heechun , Lim, Sung Kyu , Swaminathan, Madhavan

Conference Paper Issue Date2019-03-25 View16

Design-Technology Co-Optimization for Standard Cell Pin Length Modulation

Yoon, Junghyun , Park, Heechun

Conference Paper Issue Date2024-01-24 View16

Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations

Yoon, Junghyun , Park, Heechun

Conference Paper Issue Date2024-04-03 View33

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool

Chang, Kyungjoon , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2023-04-17 View15

Eliminating Minimum Implant Area Violations With Design Quality Preservation File

Jeong, Eunsol , Kim, Taewhan , Park , Heechun

Article Issue Date2023-05 View16

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