ScholarWorks: Researcher Page

BROWSE

ScholarWorks

Researcher Page

Lee, Jongeun (이종은)

Department: Department of Electrical Engineering(전기전자공학과)

Website: http://ecl.unist.ac.kr/

Lab: Intelligent Computing and Codesign Lab. (지능형 컴퓨팅 및 통합설계 연구실)

Research Keywords: Deep learning processor architecture, Quantization, Energy efficiency, Reconfigurable architecture, Compilers

Research Interests: Our research area is co-design of hardware and software for optimizing cost, performance, power, and energy of emerging computer systems. Examples of such systems include AI (Artificial Intelligence) processors and Systems-on-Chips (SoCs) for media and signal processing applications.

This table browses all dspace content
Issue Date	Title	Author(s)	Type	View	Altmetrics
2020-12	IR-QNN Framework: An IR Drop-Aware Offline Training Of Quantized Crossbar Arrays	Fouda, Mohammed E.; Lee, Sugil; Lee, Jongeun, et al	ARTICLE	90	IR-QNN Framework: An IR Drop-Aware Offline Training Of Quantized Crossbar Arrays
2020-12	Bitstream-Based Neural Network for Scalable, Efficient, and Accurate Deep Learning Hardware	Sim, Hyeonuk; Lee, Jongeun	ARTICLE	42	Bitstream-Based Neural Network for Scalable, Efficient, and Accurate Deep Learning Hardware
2020-06	RRNet: Repetition-Reduction Network for Energy Efficient Depth Estimation	Oh, Sangyun; Kim, Hye-Jin S.; Lee, Jongeun, et al	ARTICLE	106	RRNet: Repetition-Reduction Network for Energy Efficient Depth Estimation
2019-09	Cost-effective stochastic MAC circuits for deep neural networks	Sim, Hyeonuk; Lee, Jongeun	ARTICLE	226	Cost-effective stochastic MAC circuits for deep neural networks
2019-07	Mask Technique for Fast and Efficient Training of Binary Resistive Crossbar Arrays	Fouda, Mohammed E.; Lee, Sugil; Lee, Jongeun, et al	ARTICLE	237	Mask Technique for Fast and Efficient Training of Binary Resistive Crossbar Arrays
2019-05	Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs	Lee, Sugil; Kim, Daewoo; Nguyen, Dong, et al	ARTICLE	465	Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs
2018-12	An Efficient and Accurate Stochastic Number Generator Using Even-distribution Coding	Zhakatayev, Aidyn; Kim, Kyounghoon; Choi, Kiyoung, et al	ARTICLE	514	An Efficient and Accurate Stochastic Number Generator Using Even-distribution Coding
2017-12	Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures	Oh, Sangyun; Lee, Hongsik; Lee, Jongeun	ARTICLE	554	Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures
2016-08	Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces	Sim, Hyeonuk; Rahman, Atul; Lee, Jongeun	ARTICLE	482	Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces
2016-07	Mapping imperfect loops to coarse-grained reconfigurable architectures	Sim, Hyeonuk; Lee, Hongsik; Seo, Seongseok, et al	ARTICLE	793	Mapping imperfect loops to coarse-grained reconfigurable architectures
2015-12	Scalable application mapping for SIMD reconfigurable architecture	Kim, Yongjoo; Lee, Jongeun; Lee, Jinyong, et al	ARTICLE	653	Scalable application mapping for SIMD reconfigurable architecture
2014-05	Improving performance of loops on DIAM-based VLIW architectures	Lee, Jinyong; Lee, Jongwon; Paek, Yunheung, et al	ARTICLE	720	Improving performance of loops on DIAM-based VLIW architectures
2014-03	Configurable range memory for effective data reuse on programmable accelerators	Lee, Jongeun; Seo, Seongseok; Paek, Jongkyung, et al	ARTICLE	725	Configurable range memory for effective data reuse on programmable accelerators
2014-02	Design and optimization for embedded and real-time computing systems and applications	Lee, Jongeun; Goddard, Steve; Kuo, Chin-Fu	ARTICLE	715	Design and optimization for embedded and real-time computing systems and applications
2013-12	Evaluator-executor transformation for efficient pipelining of loops with conditionals	Jeong, Yeonghun; Seo, Seongseok; Lee, Jongeun	ARTICLE	646	Evaluator-executor transformation for efficient pipelining of loops with conditionals
2013-11	Software-based register file vulnerability reduction for embedded processors	Lee, Jongeun; Shrivastava, Aviral	ARTICLE	619	Software-based register file vulnerability reduction for embedded processors
2013-10	Architecture Customization of On-Chip Reconfigurable Accelerators	Yoon, Jonghee W.; Lee, Jongeun; Park, Sanghyun, et al	ARTICLE	620	Architecture Customization of On-Chip Reconfigurable Accelerators
2012-07	Return Data Interleaving for Multi-Channel Embedded CMPs Systems	Hong, Fei; Shrivastava, Aviral; Lee, Jongeun	ARTICLE	709	Return Data Interleaving for Multi-Channel Embedded CMPs Systems
2012-07	PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems	Lee, Jongeun; Shrivastava, Aviral	ARTICLE	653	PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems
2012-01	Improving Performance of Nested Loops on Reconfigurable Array Processors	Kim, Yongjoo; Lee, Jongeun; Mai, Toan X., et al	ARTICLE	665	Improving Performance of Nested Loops on Reconfigurable Array Processors

1 2

BROWSE

Researcher Page

MENU