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Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Instruction set synthesis with efficient instruction encoding for configurable processors

Cited 3 times inthomson ciCited 5 times inthomson ci
Title
Instruction set synthesis with efficient instruction encoding for configurable processors
Author
Lee, JongeunChoi, KiyoungDutt, Nikil D.
Keywords
Application-specific instruction set processor (ASIP); Bitwidth-economical; Configurable processor; Instruction encoding; ISA customization and specialization
Issue Date
2007-01
Publisher
ASSOC COMPUTING MACHINERY
Citation
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.12, no.1, pp.1 - 37
Abstract
Application-specific instructions can significantly improve the performance, energy-efficiency, and code size of configurable processors. While generating new instructions from application-specific operation patterns has been a common way to improve the instruction set (IS) of a configurable processor, automating the design of ISs for given applications poses new challenges - -how to create as well as utilize new instructions in a systematic manner, and how to choose the best set of application-specific instructions considering the various effects the new instructions may have on the data path and the compilation To address these problems, we present a novel IS synthesis framework that optimizes the IS through an efficient instruction encoding for the given application as well as for the given data path architecture. We first build a library of new instructions created with various encoding alternatives taking into account the data path architecture constraints, and then select the best set of instructions while satisfying the instruction bitwidth constraint. We formulate the problem using integer linear programming and also present an effective heuristic algorithm. Experimental results using our technique generate ISs that show improvements of up to about 40% over the native IS for several application benchmarks running on typical embedded RISC processors.
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DOI
10.1145/1188275.1188283
ISSN
1084-4309
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EE_Journal Papers
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