File Download

There are no files associated with this item.

  • Find it @ UNIST can give you direct access to the published full text of this article. (UNISTARs only)
Related Researcher

이종은

Lee, Jongeun
Intelligent Computing and Codesign Lab.
Read More

Views & Downloads

Detailed Information

Cited time in webofscience Cited time in scopus
Metadata Downloads

Instruction set synthesis with efficient instruction encoding for configurable processors

Author(s)
Lee, JongeunChoi, KiyoungDutt, Nikil D.
Issued Date
2007-01
DOI
10.1145/1188275.1188283
URI
https://scholarworks.unist.ac.kr/handle/201301/7892
Fulltext
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=33846950858
Citation
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.12, no.1, pp.1 - 37
Abstract
Application-specific instructions can significantly improve the performance, energy-efficiency, and code size of configurable processors. While generating new instructions from application-specific operation patterns has been a common way to improve the instruction set (IS) of a configurable processor, automating the design of ISs for given applications poses new challenges - -how to create as well as utilize new instructions in a systematic manner, and how to choose the best set of application-specific instructions considering the various effects the new instructions may have on the data path and the compilation To address these problems, we present a novel IS synthesis framework that optimizes the IS through an efficient instruction encoding for the given application as well as for the given data path architecture. We first build a library of new instructions created with various encoding alternatives taking into account the data path architecture constraints, and then select the best set of instructions while satisfying the instruction bitwidth constraint. We formulate the problem using integer linear programming and also present an effective heuristic algorithm. Experimental results using our technique generate ISs that show improvements of up to about 40% over the native IS for several application benchmarks running on typical embedded RISC processors.
Publisher
ASSOC COMPUTING MACHINERY
ISSN
1084-4309
Keyword (Author)
algorithmsdesignapplication-specific instruction set processor (ASIP)configurable processorISA customization and specializationinstruction encodingbitwidth-economical
Keyword
ARCHITECTURE

qrcode

Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.