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Lee, Jongeun
Intelligent Computing and Codesign Lab.
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Scalable stochastic-computing accelerator for convolutional neural networks

Author(s)
Sim, HyeonukNguyen, DongLee, JongeunChoi, Kiyoung
Issued Date
2017-01-16
DOI
10.1109/ASPDAC.2017.7858405
URI
https://scholarworks.unist.ac.kr/handle/201301/37533
Fulltext
http://ieeexplore.ieee.org/document/7858405/
Citation
22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, pp.696 - 701
Abstract
Stochastic Computing (SC) is an alternative design paradigm particularly useful for applications where cost is critical. SC has been applied to neural networks, as neural networks are known for their high computational complexity. However previous work in this area has critical limitations such as the fully-parallel architecture assumption, which prevent them from being applicable to recent ones such as convolutional neural networks, or ConvNets. This paper presents the first SC architecture for ConvNets, shows its feasibility, with detailed analyses of implementation overheads. Our SC-ConvNet is a hybrid between SC and conventional binary design, which is a marked difference from earlier SC-based neural networks. Though this might seem like a compromise, it is a novel feature driven by the need to support modern ConvNets at scale, which commonly have many, large layers. Our proposed architecture also features hybrid layer composition, which helps achieve very high recognition accuracy. Our detailed evaluation results involving functional simulation and RTL synthesis suggest that SC-ConvNets are indeed competitive with conventional binary designs, even without considering inherent error resilience of SC.
Publisher
22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
ISBN
978-150901558-0

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