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Architecture Customization of On-Chip Reconfigurable Accelerators File

Yoon, Jonghee W. , Lee, Jongeun , Park, Sanghyun , Kim, Yongjoo , Lee, Jinyong , Paek, Yunheung , Cho, Doosan

Article Issue Date2013-10 View8

Architecture exploration of standard-cell and FPGA-overlay CGRAs using the open-source CGRA-ME framework File

Chin, S. Alexander , Niu, Kuang Ping , Walker, Matthew , Yin, Shizhang , Mertens, Alexander , Lee, Jongeun , Anderson, Jason H

Conference Paper Issue Date2018-03-25 View3

Architecture of multichannel DQDB network File

Lee, JH , Lee, Jaiyong , Lee, SB

Article Issue Date1998-01 View7

Architecture of neural processing unit for deep neural networks File

Lee, Kyuho Jason

Article Issue Date2021-03 View10

Architecture, Chip, and Package Co-design Flow for 2.5D Integration of Reusable IP Chiplets

Kim, Jinwoo , Park, Heechun , Lim, Sung Kyu

Conference Paper Issue Date2019-06-02 View14

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse File

Kim, Jinwoo , Murali, Gauthaman , Park, Heechun , Qin, Eric , Kwon, Hyoukjun , Chekuri, Venkata Chaitanya Krishna , Rahman, Nael Mizanur , Dasari, Nihar , Singh, Arvind , Lee, Minah , et al

Article Issue Date2020-11 View17

Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor File

Lee, Segi , Lee, Sugil , Lee, Jongeun , Choi, Jong-Moon , Kwon, Do-Wan , Hong, Seung-Kwang , Kwon, Kee-Won

Conference Paper Issue Date2020-09-07 View6

Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor File File

LEE, Se Gi

Thesis Issue Date2020-08 View13

Are Analog and Mixed Mode Circuits the Future Solution of AI SoCs?

Lee, Kyuho Jason

Conference Paper Issue Date2019-11-05 View10

Area and Power Efficient 10-Bit Column Driver with 67-MS/s Time-Dividing DAC and Output Buffer Sharing for Mobile Active-Matrix OLEDs File File

Yoon, Rae-Hwan

Thesis Issue Date2021-02 View3

Area-Efficient, Ultra-Low Jitter Clock Generators Using Injection Locking Techniques File

Choi, Seojin

Thesis Issue Date2020-08 View10

Array configuration optimisation of dual-band controlled reception pattern antenna arrays for anisotropic ground platforms File

Byun, Gangil , Choo, Hosung , Kim, Sunwoo

Article Issue Date2014-06 View7

Array configuration optimization using an objective function for accurate DOA estimation File

Byun, Gangil , Joo, Jeungmin , Kim, Kichul , Seo, Seungmo , Kim, Sunwoo , Choo, Hosung

Conference Paper Issue Date2013-11-05 View4

Artificial Intelligence Meets Autonomy in Wireless Networks: A Distributed Learning Approach File

Lee, Hoon , Lee, Sang Hyun , Quek, Tony Q. S.

Article Issue Date2022-11 View13

Artificial multimodal receptors based on ion relaxation dynamics File

You, Insang , Mackanic, David G. , Matsuhisa, Naoji , Kang, Jiheong , Kwon, Jimin , Beker, Levent , Mun, Jaewan , Suh, Wonjeong , Kim, Tae Yeong , Tok, Jeffrey B-H , et al

Article Issue Date2020-11 View7

Asymmetric Iris Structures for Dual-Polarization Waveguide Slot Arrays for E-Band Wireless Backhaul Systems File

You, Sion , Ahn, Sang Chul , Kim, Young Su , Byun, Gangil

Article Issue Date2022-04 View9

Asymmetric mixed modular multilevel converter topology in bipolar HVDC transmission systems

Jung, J. J , Lee, Joon-Hee , Sul, S. K

Conference Paper Issue Date2017-10-01 View10

Asymmetric Mixed Modular Multilevel Converter Topology in Hybrid Bipolar HVDC Transmission Systems

Lee, Joon-Hee , Jung, J. J , Sul, S. K

Conference Paper Issue Date2018-05-20 View13

Asymmetry-Aware Real-Time Distributed Joint Resource Allocation in IEEE 802.22 WRANs File

Kim, Hyoil , Shin, Kang G.

Conference Paper Issue Date2010-03-16 View4

Asymptotically optimal optical orthogonal codes with new parameters File

Chung, Jin-Ho , Yang, Kyeongcheol

Article Issue Date2013-06 View7

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