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- Jeong, Hongsik
- Future Semiconductor Technology Lab.
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A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM
- Author(s)
- Yoon, Hongil, Cha, Gi-Won, Yoo, Changsik, Kim, Nam-Jong, Kim, Keum-Yong, Lee, Chang Ho, Lim, Kyu-Nam, Lee, Kyuchan, Jeon, Jun-Young, Jung, Tae Sung, Jeong, Hongsik, Chung, Tae-Young, Kim, Kinam, Cho, Soo In
- Issued Date
- 1999-11
- DOI
- 10.1109/4.799867
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.34, no.11, pp.1589 - 1599
- Abstract
- A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-mu m process, The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- ISSN
- 0018-9200
- Keyword (Author)
- CMOS, delay locked loop (DLL), double data rate (DDR), DRAM, low voltage, phase detector, SDRAM, wave pipeline
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