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DC Field | Value | Language |
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dc.citation.endPage | 1599 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 1589 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 34 | - |
dc.contributor.author | Yoon, Hongil | - |
dc.contributor.author | Cha, Gi-Won | - |
dc.contributor.author | Yoo, Changsik | - |
dc.contributor.author | Kim, Nam-Jong | - |
dc.contributor.author | Kim, Keum-Yong | - |
dc.contributor.author | Lee, Chang Ho | - |
dc.contributor.author | Lim, Kyu-Nam | - |
dc.contributor.author | Lee, Kyuchan | - |
dc.contributor.author | Jeon, Jun-Young | - |
dc.contributor.author | Jung, Tae Sung | - |
dc.contributor.author | Jeong, Hongsik | - |
dc.contributor.author | Chung, Tae-Young | - |
dc.contributor.author | Kim, Kinam | - |
dc.contributor.author | Cho, Soo In | - |
dc.date.accessioned | 2023-12-22T12:09:35Z | - |
dc.date.available | 2023-12-22T12:09:35Z | - |
dc.date.created | 2019-07-11 | - |
dc.date.issued | 1999-11 | - |
dc.description.abstract | A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-mu m process, The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated. | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.34, no.11, pp.1589 - 1599 | - |
dc.identifier.doi | 10.1109/4.799867 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.scopusid | 2-s2.0-0033221599 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/27118 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/799867 | - |
dc.identifier.wosid | 000083453700020 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Engineering | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | delay locked loop (DLL) | - |
dc.subject.keywordAuthor | double data rate (DDR) | - |
dc.subject.keywordAuthor | DRAM | - |
dc.subject.keywordAuthor | low voltage | - |
dc.subject.keywordAuthor | phase detector | - |
dc.subject.keywordAuthor | SDRAM | - |
dc.subject.keywordAuthor | wave pipeline | - |
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