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Kim, Seong-Jin
Bio-inspired Microsystems Lab (BiML)
Research Interests
  • Integrated analog-mixed signal circuit design, semiconductor sensor interface circuits


Tunnelling-based ternary metal–oxide–semiconductor technology

DC Field Value Language Jeong, Jae Won ko Choi, Young Eun ko Kim, Woo Seok ko Park, Jee-Ho ko Kim, Sunmean ko Shin, Sunhae ko Lee, Kyuho ko Chang, Jiwon ko Kim, Seong-Jin ko Kim, Kyung Rok ko 2019-07-10T09:19:10Z - 2019-07-04 ko 2019-07 ko
dc.identifier.citation NATURE ELECTRONICS, v.2, no.7, pp.307 - 3112 ko
dc.identifier.issn 2520-1131 ko
dc.identifier.uri -
dc.description.abstract The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. ko
dc.language 영어 ko
dc.title Tunnelling-based ternary metal–oxide–semiconductor technology ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-85069442467 ko
dc.type.rims ART ko
dc.identifier.doi 10.1038/s41928-019-0272-8 ko
dc.identifier.url ko
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