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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 3112 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 307 | - |
dc.citation.title | NATURE ELECTRONICS | - |
dc.citation.volume | 2 | - |
dc.contributor.author | Jeong, Jae Won | - |
dc.contributor.author | Choi, Young Eun | - |
dc.contributor.author | Kim, Woo Seok | - |
dc.contributor.author | Park, Jee-Ho | - |
dc.contributor.author | Kim, Sunmean | - |
dc.contributor.author | Shin, Sunhae | - |
dc.contributor.author | Lee, Kyuho | - |
dc.contributor.author | Chang, Jiwon | - |
dc.contributor.author | Kim, Seong-Jin | - |
dc.contributor.author | Kim, Kyung Rok | - |
dc.date.accessioned | 2023-12-21T19:02:35Z | - |
dc.date.available | 2023-12-21T19:02:35Z | - |
dc.date.created | 2019-07-04 | - |
dc.date.issued | 2019-07 | - |
dc.description.abstract | The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. | - |
dc.identifier.bibliographicCitation | NATURE ELECTRONICS, v.2, no.7, pp.307 - 3112 | - |
dc.identifier.doi | 10.1038/s41928-019-0272-8 | - |
dc.identifier.issn | 2520-1131 | - |
dc.identifier.scopusid | 2-s2.0-85069442467 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/26858 | - |
dc.identifier.url | https://www.nature.com/articles/s41928-019-0272-8 | - |
dc.identifier.wosid | 000476813900012 | - |
dc.language | 영어 | - |
dc.publisher | NATURE PUBLISHING GROUP | - |
dc.title | Tunnelling-based ternary metal–oxide–semiconductor technology | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Engineering | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | MULTIPLE-VALUED LOGIC | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | MOSFETS | - |
dc.subject.keywordPlus | FETS | - |
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