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Showing results 6 to 16 of 16

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool

Chang, Kyungjoon , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2023-04-17 View16
Eliminating Minimum Implant Area Violations With Design Quality Preservation File

Jeong, Eunsol , Kim, Taewhan , Park , Heechun

Article Issue Date2023-05 View19
Fault Coverage and Resource Analysis for Diverse Structures of Clock TSV Fault-Tolerant Units in 3D ICs

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2013-11-17 View10
Hybrid asynchronous circuit generation amenable to conventional EDA flow File

Park , Heechun , Kim, Taewhan

Article Issue Date2019-01 View19
Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement

Jeong, Eunsol , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2021-08-09 View10
Size-dependent antibiotic effect of graphene oxide

Kim, Ungsoo , Park, Kwang Hyun , Lee, Junghyun , Kim, Taewhan , Kwon, Heeyun , Mitchell, Robert J. , Yang, Changduk , Park, Hyesung

Conference Paper Issue Date2017-04-06 View15
Speeding-up neuromorphic computation for neural networks: Structure optimization approach File

Park , Heechun , Kim, Taewhan

Article Issue Date2022-01 View18
Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Networks

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2018-03-19 View19
Synthesis of TSV Fault-Tolerant 3-D Clock Trees File

Park, Heechun , Kim, Taewhan

Article Issue Date2015-02 View22
Synthesizing Asynchronous Circuits Toward Practical Use File

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2016-07-11 View18
비동기식 회로 설계 구조에 대한 전력 및 면적 비교

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2015-11-27 View15
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