Modeling of Through-Silicon Via (TSV) Interposer Considering Depletion Capacitance and Substrate Layer Thickness Effects
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- Modeling of Through-Silicon Via (TSV) Interposer Considering Depletion Capacitance and Substrate Layer Thickness Effects
- Han, Ki Jin; Swaminathan, Madhavan; Jeong, Jongwoo
- Issue Date
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.5, no.1, pp.108 - 118
- To support the recent progress in 3-D integration based on through-silicon via (TSV) technology, an improved electromagnetic modeling method for TSVs is presented. In the framework of the mixed-potential integral equations combined with cylindrical modal basis functions, the proposed method can extract the effects of depletion capacitances and a finite substrate. To include the effects of depletion region generated by an external dc bias voltage, an additional capacitive cell is employed around a TSV. The proposed method also considers the effect from the finite silicon substrate accurately by employing the multilayered Green's functions. To reduce the computational cost for calculations involving Green's functions, a method to approximate Green's functions over localized intervals when computing partial potential coefficients is presented. The proposed method is validated for simple TSV examples and shows an improved accuracy with the acceptable usage of memory and simulation time. In addition, a 10 x 10 TSV array is modeled using different design parameters, showing the capability for dealing with larger size problems using this method.
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