BROWSE

Related Researcher

Author's Photo

Han, Ki Jin
Electromagnetic System Design Lab
Research Interests
  • Electromagnetics, electromechanics, electromagnetic compatibility (EMC)

ITEM VIEW & DOWNLOAD

Modeling of Through-Silicon Via (TSV) Interposer Considering Depletion Capacitance and Substrate Layer Thickness Effects

DC Field Value Language
dc.contributor.author Han, Ki Jin ko
dc.contributor.author Swaminathan, Madhavan ko
dc.contributor.author Jeong, Jongwoo ko
dc.date.available 2015-01-06T00:00:05Z -
dc.date.created 2015-01-05 ko
dc.date.issued 2015-01 ko
dc.identifier.citation IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.5, no.1, pp.108 - 118 ko
dc.identifier.issn 2156-3950 ko
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/9812 -
dc.description.abstract To support the recent progress in 3-D integration based on through-silicon via (TSV) technology, an improved electromagnetic modeling method for TSVs is presented. In the framework of the mixed-potential integral equations combined with cylindrical modal basis functions, the proposed method can extract the effects of depletion capacitances and a finite substrate. To include the effects of depletion region generated by an external dc bias voltage, an additional capacitive cell is employed around a TSV. The proposed method also considers the effect from the finite silicon substrate accurately by employing the multilayered Green's functions. To reduce the computational cost for calculations involving Green's functions, a method to approximate Green's functions over localized intervals when computing partial potential coefficients is presented. The proposed method is validated for simple TSV examples and shows an improved accuracy with the acceptable usage of memory and simulation time. In addition, a 10 x 10 TSV array is modeled using different design parameters, showing the capability for dealing with larger size problems using this method. ko
dc.description.statementofresponsibility close -
dc.language 영어 ko
dc.publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC ko
dc.title Modeling of Through-Silicon Via (TSV) Interposer Considering Depletion Capacitance and Substrate Layer Thickness Effects ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-85027943232 ko
dc.identifier.wosid 000348123200013 ko
dc.type.rims ART ko
dc.description.wostc 1 *
dc.description.scopustc 1 *
dc.date.tcdate 2015-12-28 *
dc.date.scptcdate 2015-11-04 *
dc.identifier.doi 10.1109/TCPMT.2014.2372771 ko
dc.identifier.url https://ieeexplore.ieee.org/document/6975150 ko
Appears in Collections:
EE_Journal Papers
Files in This Item:
There are no files associated with this item.

find_unist can give you direct access to the published full text of this article. (UNISTARs only)

Show simple item record

qrcode

  • mendeley

    citeulike

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

MENU