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김명수

Kim, Myungsoo
Nano Electronics and Technology Lab.
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On-Chip Direct Synthesis of 2D Semimetals for van der Waals Metal–Semiconductor Junction Transistor Arrays

Author(s)
Yang, JihoonIm, JaehongKim, JaeminLee, HyeonwooPark, JaeeunLee, SeungchanLee, JiyeonKim, Byeong KyuKim, MyungsooYoo, Jung-WooLee, ZonghoonKwon, Soon-Yong
Issued Date
2026-03
DOI
10.1021/acsnano.5c20543
URI
https://scholarworks.unist.ac.kr/handle/201301/91249
Fulltext
https://pubs.acs.org/doi/10.1021/acsnano.5c20543
Citation
ACS Nano
Abstract
Metallic two-dimensional (2D) materials enable van der Waals (vdW) contacts that suppress metal- and defectinduced gap states via an intrinsic interlayer gap; however, their conventional integration through film transfer or high-temperature chemical vapor deposition often damages the underlying 2D semiconductors. Here, we report a low-temperature (350 °C), transferfree approach to form all-2D metal−semiconductor junctions with atomically clean vdW interfaces. A predeposited chalcogen layer (Te or Se) on 2H-MoTe2 acts as both a reactive precursor and an encapsulation layer during patterned deposition of transition metals (Mo or Pt). Upon annealing at 350 °C, the chalcogen/transition-metal stack is converted in situ into metallic 2D electrodes (1T′-MoTe2, 1T-PtTe2, or 1T-PtSe2), yielding damage-free vdW contacts. The resulting 2D transistor arrays exhibit efficient hole injection, high mobility (∼24 cm2 /V·s), low contact resistance, and ultralow Schottky barriers (∼31 meV), with device-to-device variation below 3.7%. These metrics were consistently reproduced across large-area device arrays, underscoring integration uniformity and scalability. This scalable, low-temperature integration approach enables the uniform formation of metallic 2D contacts and reliable 2D FET operation across large-area device arrays.
Publisher
AMER CHEMICAL SOC
ISSN
1936-0851

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