Cited time in
Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.citation.title | ACS Nano | - |
| dc.contributor.author | Yang, Jihoon | - |
| dc.contributor.author | Im, Jaehong | - |
| dc.contributor.author | Kim, Jaemin | - |
| dc.contributor.author | Lee, Hyeonwoo | - |
| dc.contributor.author | Park, Jaeeun | - |
| dc.contributor.author | Lee, Seungchan | - |
| dc.contributor.author | Lee, Jiyeon | - |
| dc.contributor.author | Kim, Byeong Kyu | - |
| dc.contributor.author | Kim, Myungsoo | - |
| dc.contributor.author | Yoo, Jung-Woo | - |
| dc.contributor.author | Lee, Zonghoon | - |
| dc.contributor.author | Kwon, Soon-Yong | - |
| dc.date.accessioned | 2026-04-07T10:03:32Z | - |
| dc.date.available | 2026-04-07T10:03:32Z | - |
| dc.date.created | 2026-03-14 | - |
| dc.date.issued | 2026-03 | - |
| dc.description.abstract | Metallic two-dimensional (2D) materials enable van der Waals (vdW) contacts that suppress metal- and defectinduced gap states via an intrinsic interlayer gap; however, their conventional integration through film transfer or high-temperature chemical vapor deposition often damages the underlying 2D semiconductors. Here, we report a low-temperature (350 °C), transferfree approach to form all-2D metal−semiconductor junctions with atomically clean vdW interfaces. A predeposited chalcogen layer (Te or Se) on 2H-MoTe2 acts as both a reactive precursor and an encapsulation layer during patterned deposition of transition metals (Mo or Pt). Upon annealing at 350 °C, the chalcogen/transition-metal stack is converted in situ into metallic 2D electrodes (1T′-MoTe2, 1T-PtTe2, or 1T-PtSe2), yielding damage-free vdW contacts. The resulting 2D transistor arrays exhibit efficient hole injection, high mobility (∼24 cm2 /V·s), low contact resistance, and ultralow Schottky barriers (∼31 meV), with device-to-device variation below 3.7%. These metrics were consistently reproduced across large-area device arrays, underscoring integration uniformity and scalability. This scalable, low-temperature integration approach enables the uniform formation of metallic 2D contacts and reliable 2D FET operation across large-area device arrays. | - |
| dc.identifier.bibliographicCitation | ACS Nano | - |
| dc.identifier.doi | 10.1021/acsnano.5c20543 | - |
| dc.identifier.issn | 1936-0851 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/91249 | - |
| dc.identifier.url | https://pubs.acs.org/doi/10.1021/acsnano.5c20543 | - |
| dc.identifier.wosid | 001715409300001 | - |
| dc.language | 영어 | - |
| dc.publisher | AMER CHEMICAL SOC | - |
| dc.title | On-Chip Direct Synthesis of 2D Semimetals for van der Waals Metal–Semiconductor Junction Transistor Arrays | - |
| dc.type | Article | - |
| dc.description.isOpenAccess | TRUE | - |
| dc.type.docType | Article | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
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