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- Yoon, Heein
- Advanced Circuits and Electronics Lab.
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An area-efficient, DTC-less fractional-N sampling PLL achieving 140 fs RMS jitter and −66.3 dBc fractional spur
- Author(s)
- An, Hyogyoung, Nam, Hyeonjun, An, Changmin, Yoon, Heein
- Issued Date
- 2025-11-03
- Citation
- IEEE Asian Solid-State Circuit Conference (ASSCC)
- Publisher
- IEEE
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