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- Yoon, Heein
- Advanced Circuits and Electronics Lab.
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | KO | - |
| dc.citation.title | IEEE Asian Solid-State Circuit Conference (ASSCC) | - |
| dc.contributor.author | An, Hyogyoung | - |
| dc.contributor.author | Nam, Hyeonjun | - |
| dc.contributor.author | An, Changmin | - |
| dc.contributor.author | Yoon, Heein | - |
| dc.date.accessioned | 2025-08-18T13:30:00Z | - |
| dc.date.available | 2025-08-18T13:30:00Z | - |
| dc.date.created | 2025-08-16 | - |
| dc.date.issued | 2025-11-03 | - |
| dc.identifier.bibliographicCitation | IEEE Asian Solid-State Circuit Conference (ASSCC) | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/87725 | - |
| dc.publisher | IEEE | - |
| dc.title | An area-efficient, DTC-less fractional-N sampling PLL achieving 140 fs RMS jitter and −66.3 dBc fractional spur | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2025-11-02 | - |
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