First Demonstration of Top-Gate Enhancement- Mode ALD In2O3 FETs With High Thermal Budget of 600 °°C for DRAM Applications

Abstract

In this work, for the first time, we report top-gate In2O3 FETs with enhancement-mode (E-mode) operation and a high thermal budget of 600 degrees C, being compatible with dynamic random-access memory (DRAM) fabrication which requires high-temperature processes ( >550 degrees C). The robustness of n(2)O(3) channel under high-temperature treatment is confirmed by transmission electron microscope (TEM) and good electrical characteristics of drain current of 350 mu A/mu m (at V-DS = 2 V), threshold voltage (V-T) similar to 1 V, and low off-current similar to 10(-14) A/ mu m determined by measurement detection limit in scaled devices with a channel length of 100 nm. Reliability characteristics of the devices are found to change with different process temperatures and can be explained by the proposed trap distribution model at the dielectric/n(2)O(3) interface. This research indicates that top-gate E-mode n(2)O(3) FETs with high-thermal budget and ultra-low off-current could find their promise to replace single crystal silicon channel for next-generation DRAM technology.