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Han, Ki Jin
Electromagnetic System Design Lab
Research Interests
  • Electromagnetics, electromechanics, electromagnetic compatibility (EMC)

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Rigorous Electrical Modeling of Through Silicon Vias (TSVs) with MOS Capacitance Effects

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Title
Rigorous Electrical Modeling of Through Silicon Vias (TSVs) with MOS Capacitance Effects
Author
Bandyopadhyay, TapobrataHan, Ki JinChung, DaehyunChatterjee, RitwikSwaminathan, MadhavanTummala, Rao
Keywords
3-D integration; interconnection modeling; parametric study; power distribution network; through silicon via; variable capacitance
Issue Date
2011-06
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.1, no.6, pp.893 - 903
Abstract
3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.
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DOI
10.1109/TCPMT.2011.2120607
ISSN
2156-3950
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EE_Journal Papers
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