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Choi, Jaehyouk
Integrated Circuits and Systems Lab (ICSL)
Research Interests
  • RF/Analog/Mixed IC design, low power CMOS IC, wired/wireless TRX IC, clock generation IC

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A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL

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Title
A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL
Author
Choi, JaehyoukKim, WoonyunLim, Kyutae
Keywords
Edge interpolator; phase locked loop (PLL); reference spur
Issue Date
2012-05
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.5, pp.969 - 973
Abstract
This paper proposes a new reference-spur elimination architecture for a charge-pump-based phase locked loop (PLL) using an edge interpolation technique. By utilizing a charge-distribution mechanism on the control voltage of the voltage-controlled oscillator, the proposed architecture is capable of suppressing high-order harmonics of the reference spur, as well as a fundamental spur. In implementation, the eight-stage edge interpolator achieved more than 16-dB additional spur suppression. In addition, the harmonics of the reference spur within a 104-MHz frequency offset, the location of the eighth harmonic of the reference spur, were dramatically suppressed. The prototype PLL was fully integrated in a 0.18-mu m CMOS technology, which occupies a 670 mu m x 640 mu m active chip area. Additional circuits for the edge interpolator consumes less than one-fifth of the total area and power.
URI
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DOI
10.1109/TVLSI.2011.2129602
ISSN
1063-8210
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EE_Journal Papers
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