A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL
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- A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL
- Choi, Jaehyouk; Kim, Woonyun; Lim, Kyutae
- Edge interpolator; phase locked loop (PLL); reference spur
- Issue Date
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.5, pp.969 - 973
- This paper proposes a new reference-spur elimination architecture for a charge-pump-based phase locked loop (PLL) using an edge interpolation technique. By utilizing a charge-distribution mechanism on the control voltage of the voltage-controlled oscillator, the proposed architecture is capable of suppressing high-order harmonics of the reference spur, as well as a fundamental spur. In implementation, the eight-stage edge interpolator achieved more than 16-dB additional spur suppression. In addition, the harmonics of the reference spur within a 104-MHz frequency offset, the location of the eighth harmonic of the reference spur, were dramatically suppressed. The prototype PLL was fully integrated in a 0.18-mu m CMOS technology, which occupies a 670 mu m x 640 mu m active chip area. Additional circuits for the edge interpolator consumes less than one-fifth of the total area and power.
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