A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
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- A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
- Oh, Tae-Young; Sohn, Young-Soo; Bae, Seung-Jun; Park, Min-Sang; Lim, Ji-Hoon; Cho, Yong-Ki; Kim, Dae-Hyun; Kim, Dong-Min; Kim, Hye-Ran; Kim, Hyun-Joong; Kim, Jin-Hyun; Kim, Jingook; Kim, Young-Sik; Kim, Byeong-Cheol; Kwak, Sang-Hyup; Lee, Jae-Hyung; Lee, Jae-Young; Shin, Chang-Ho; Yang, Yunseok; Cho, Beom-Sig; Bang, Sam-Young; Yang, Hyang-Ja; Choi, Young-Ryeol; Moon, Gil-Shin; Park, Cheol-Goo; Hwang, Seok-Won; Lim, Jeong-Don; Park, Kwang-Il; Choi, Joo Sun; Jun, Young-Hyun
- Active jitter canceller; bank group; bank to bank active time; bitline sense amplifier enable; core cycle; GDDR5; IO sense amplifier auto calibration; low latency VPP generator; page hit rate; replica impedance monitor; skewed logic; tRRD
- Issue Date
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.46, no.1, pp.107 - 118
- This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller. This GDDR5 SDRAM was fabricated in 50 nm standard DRAM process in 61.6 mm2 die area and operates with 1.5 V power supply.
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