File Download

There are no files associated with this item.

  • Find it @ UNIST can give you direct access to the published full text of this article. (UNISTARs only)
Related Researcher

김진국

Kim, Jingook
Integrated Circuit and Electromagnetic Compatibility Lab.
Read More

Views & Downloads

Detailed Information

Cited time in webofscience Cited time in scopus
Metadata Downloads

Full metadata record

DC Field Value Language
dc.citation.endPage 118 -
dc.citation.number 1 -
dc.citation.startPage 107 -
dc.citation.title IEEE JOURNAL OF SOLID-STATE CIRCUITS -
dc.citation.volume 46 -
dc.contributor.author Oh, Tae-Young -
dc.contributor.author Sohn, Young-Soo -
dc.contributor.author Bae, Seung-Jun -
dc.contributor.author Park, Min-Sang -
dc.contributor.author Lim, Ji-Hoon -
dc.contributor.author Cho, Yong-Ki -
dc.contributor.author Kim, Dae-Hyun -
dc.contributor.author Kim, Dong-Min -
dc.contributor.author Kim, Hye-Ran -
dc.contributor.author Kim, Hyun-Joong -
dc.contributor.author Kim, Jin-Hyun -
dc.contributor.author Kim, Jingook -
dc.contributor.author Kim, Young-Sik -
dc.contributor.author Kim, Byeong-Cheol -
dc.contributor.author Kwak, Sang-Hyup -
dc.contributor.author Lee, Jae-Hyung -
dc.contributor.author Lee, Jae-Young -
dc.contributor.author Shin, Chang-Ho -
dc.contributor.author Yang, Yunseok -
dc.contributor.author Cho, Beom-Sig -
dc.contributor.author Bang, Sam-Young -
dc.contributor.author Yang, Hyang-Ja -
dc.contributor.author Choi, Young-Ryeol -
dc.contributor.author Moon, Gil-Shin -
dc.contributor.author Park, Cheol-Goo -
dc.contributor.author Hwang, Seok-Won -
dc.contributor.author Lim, Jeong-Don -
dc.contributor.author Park, Kwang-Il -
dc.contributor.author Choi, Joo Sun -
dc.contributor.author Jun, Young-Hyun -
dc.date.accessioned 2023-12-22T06:37:17Z -
dc.date.available 2023-12-22T06:37:17Z -
dc.date.created 2014-10-29 -
dc.date.issued 2011-01 -
dc.description.abstract This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller. This GDDR5 SDRAM was fabricated in 50 nm standard DRAM process in 61.6 mm2 die area and operates with 1.5 V power supply. -
dc.identifier.bibliographicCitation IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.46, no.1, pp.107 - 118 -
dc.identifier.doi 10.1109/JSSC.2010.2085991 -
dc.identifier.issn 0018-9200 -
dc.identifier.scopusid 2-s2.0-78650867466 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/7969 -
dc.identifier.url http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=78650867466 -
dc.identifier.wosid 000285839200011 -
dc.language 영어 -
dc.publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC -
dc.title A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction -
dc.type Article -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -

qrcode

Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.